A Study of Next Generation CFET Process Integration Options

Decision making is a critical step in semiconductor technology development. R&D semiconductor engineers must consider different design and process options early in the development of a next-generation technology. Established techniques such as Failure Mode and Effect Analysis (FMEA) can be used to select among the most promising design and process choices. Once specific design and process methodologies are chosen, time and money is then spent on first tape-out and wafer processing.

How can engineers ensure that they have selected the optimal design and technology development pathway prior to tape-out? How do they know that critical technology decisions were made properly?

Often, a semiconductor process/layout option is selected based upon the best and lowest cost method to achieve a nominal targeted performance. Unfortunately, inherent variations in a process step are rarely considered as part of this technology decision-making process, even though these variations can be a critical factor in the success of a semiconductor development project. The effect of process variability is often only considered during the ramp-up phase of technology development. This lack of foresight can be expensive, since design and process changes needed to compensate for unexpected variability can be costly during later stages of technology developments. At the IEEE-S3S (SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY) conference in October 2019, a team from Coventor and imec presented an example of using SEMulator3D^® virtual fabrication to improve technology decision making through early consideration of process variability.

The presentation discussed three different ways of fabricating Complementary-Field Effect Transistors (CFETs). In Figure 1, a CFET architecture example consisting of 2 Nanowire Field Effect Transistors (p-type) on top of 2 Fin Field Effect Transistors (n-type) is shown. Note that an n- on p- type CFET could have also been considered for this study. For additional background information on CFET transistor technology, please read our blog “Practical Methods to Overcome the Challenges of 3D Logic Design”.

In the IEEE-S3S presentation, different process flow options were benchmarked for a CFET device to determine the most robust option with respect to process variability [1].  We compared the reliability of 3 different process flow options for the CFET, using 3 different substrates: bulk Si, Silicon-On-Insulator (SOI), or a Double Silicon-On-Insulator (DSOI).

In this study, we tested hundreds of virtual wafers for each of the process flows. The study was performed without requiring the fabrication of any actual test wafers. We included delta-to-target (variability) in our experiment for a number of parameters, such as film thickness, etch depth, etc. In the virtual experiment, we then identified key potential failure modes and determined the most robust process flow with respect to pre-defined variation assumptions (1, 2 and 3%). The results of this experiment are shown in Figure 2.

With the same magnitude of process variation applied to each of the process flows (substrates), the authors were able to identify the optimal design and technology pathway. In this instance, SOI was the most robust starting material under equivalent process variation assumptions, with the lowest probability of specific failures related to CFET fabrication.

If you wish to learn more about this study, please download the full paper “A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates“.

Reference:

[1] B. Vincent et al., A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates, S3S conference, Oct 2019