It seems like yesterday that FinFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of FinFETs began at the 22 nm node and has continued through the 7 nm node. Beyond 7 nm, it looks like nanosheet device structures will be used for at least the 5 nm and probably the 3 nm nodes. The nanosheet device structure is the brainchild of IBM [1], and eloquently turns the FinFET structure on its side and then stacks a few of these nanosheets one on top of each another. This increases the effective device width per active footprint area, and ultimately the available drive current. Figure 1 shows the evolution of a nanosheet structure from a double stack structure to an optimized single stack structure. Figure 2 displays the improvement in Weff (total effective width) at a fixed active region width, comparing an extremely scaled FinFET to an optimized single nanosheet stack containing 3 levels.
Fig. 1: Nanosheet evolution [1]
Fig. 2: Improvement in Weff per fixed footprint [1]
Optimizing nanosheet performance requires careful design of the nanosheet width (Dwire), the nanosheet thickness (Twire), and the nanosheet spacing (Tsus), as shown in Fig. 3. Figure 4 displays the resulting device electrical characteristics for both FinFET and nanosheet devices. With careful optimization of geometry, nanosheets outperform FinFETs both electrostatically and with respect to Ion/Ioff performance (Fig. 4). Even with potentially higher total Ceff (effective capacitance), the nanosheet AC frequency performance also improves upon its FinFET predecessor (Fig.5)
Fig. 3: Nanosheet Geometry [2]
Fig. 4: Electrical Characteristics: FinFET vs Nanosheet [2]
Fig. 5: AC Frequency Comparison [2]
When we consider the 3 nm node and beyond, the preferred device architecture may evolve yet again, from a nanosheet to a stacked forksheet architecture [3]. The stacked forksheet device is similar to the nanosheet device, only now the nFET and pFET devices are next to each other and separated by a dielectric wall that greatly reduces n-to-p spacing. Researchers at IMEC have quantified the power-performance advantage of the forksheet structure using their 2 nm technology node. They have demonstrated a 10% speed advantage at constant power, and a 24% power reduction at constant speed [4] compared to a nanosheet device. This performance gain is achieved by a combination of reduced CMiller capacitance (due to a smaller gate-drain overlap), and the ability to increase the sheet width to improve drive current.
Fig. 6: Evolutionary path from FinFET to Forksheet [4]
As we scale to 3 nm and beyond, BEOL interconnect technology must also scale to take advantage of the power-performance improvements created by these new device structures. The BEOL interconnects need to provide low wire and via resistance, in order to ensure power efficiency and meet reliability requirements at the smaller line widths. The dual damascene interconnect process has been the BEOL workhorse for multiple technology generations up to the present time, but may have future scaling issues. Until recently, copper has been the metal of choice for interconnects, but as we continue to scale towards smaller and smaller metal pitches it is being challenged from both a resistance and reliability point of view. Copper liner requirements limit the ability to scale this metal to smaller dimensions. This limitation has increased research into replacing copper with alternative metals such as Co, Ru, and Mo at the local metal levels. Hybrid metallization or via prefill are other technology options being explored to scale BEOL interconnects (see Fig. 7).
Fig. 7: Hybrid metallization: Via prefill [5]
Beyond the choice of metal, the process of forming metal interconnects at a 20 nm pitch is also being researched. The scaling limits of dual damascene have led to a renewed interest in subtractive metal etch, or a semi-damascene process. In this approach, a via is etched into the dielectric, then overfilled with metal. The metal is then patterned and etched directly on the wafer. The etch limitations of Cu will require that other metals (e.g. Ru or Mo) will also need to be considered in the semi-damascene process. There are many potential issues with a semi-damascene process flow. These include a more challenging alignment process (since it is difficult to see the alignment marks once the wafer is covered in metal), along with metal etch and LER (line edge roughness) issues. However, a semi-damascene process flow also has a number of advantages. These advantages include:
The potential to increase the aspect ratio of the metal lines, which can lead to lower resistance
The ability to incorporate air gaps between the metal lines, which can significantly reduce capacitance [5].
Overall, the road to 3 nm and beyond is filled with exciting opportunities in both device structure and BEOL interconnect schemes. The goal, of course, is to maximize chip performance while minimizing chip power dissipation, process complexity and cost. This is an extremely challenging problem, and will require significant research in process and device modeling, process integration, and wafer fabrication to determine the best options. This work will hopefully lead to the commercialization of next-generation nanosheet and forksheet structures, as we advance to the 3 nm node and beyond.
References:
N. Loubet, et al., Symposium on VLSI Technology (2017).
S-D. Kim, et al., IEEE SOI-3D-Subthreshold Conf. (2015).
Michael Hargrove is a member of the semiconductor process and integration team at Coventor, a Lam Research Company. He has worked in the semiconductor technology development business for more than 30 years. He began his career at IBM, where he worked on advanced CMOS technology development. He then spent five years at Epson Research and Development, working on high-speed/high-frequency device design and characterization. He later joined AMD, where he worked on high-k/metal gate technology. Hargrove subsequently transitioned to GlobalFoundries Research and Development in Albany, NY. At Coventor his focus is 3D semiconductor process modeling. Hargrove received his Ph.D. from the Thayer School of Engineering at Dartmouth College, in Hanover, N.H.
Figure 2: A test structure designed to calculate capacitance using 2 nets. The 2 separate nets have 6 ports (P1-P6) and 4 ports (P7-P10), respectively.
