By: David Fried, Ph.D., Chief Technology Officer, Semiconductor

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We asked our panelists questions such as:

1. What is BEOL? Where does it begin and end?
2. Are there fundamental limits to interconnect processes? How much longer can we continue to use current interconnect processes and technologies?
3. What changes are required at 5nm and beyond? Is there a single solution, or are multiple changes required such as new materials, equipment, integration schemes, device layouts? When will current patterning, metallization and other processes fail to scale to the next node?
4. If we continue to scale interconnect dimensions, will we create yield, reliability, cost or manufacturing challenges that prove insurmountable?
5. Does 3D integration (TSVs, die-stacking, etc.) change this discussion?
6 . What new patterning techniques (like EUV) might help, and where do you introduce these new techniques?
7. Can we extend current materials and tools to 10nm, 7nm and beyond, or do we need something else?

Our panelists included Craig Child, senior manager and deputy director for GlobalFoundries’ ATD integration unit; Paul Besser, senior technology director at Lam Research; David Fried, CTO at Coventor; Chih Chien Liu, deputy division director for UMC’s ATD Module Division; and Anton deVilliers, director of patterning technology and SMTS at Tokyo Electron. The panel was moderated by Ed Sperling, Editor in Chief of Semiconductor Engineering

The discussion started with a definition of where BEOL begins and ends, with some panelists noting that the middle of line and BEOL boundaries are beginning to blur. Issues and solutions with RC delay, including yield and reliability problems, were brought up early in the discussion. Panelists noted that current techniques to decrease feature size are leading to higher complexity, count and cost for BEOL layers and masks.

The panelists discussed new architectures such as nanowires, 3D and other architectural advances, and how these have affected device density and device cost. The issues and benefits of 3D devices were definitely a topic of interest, but panelists noted that 3D devices have patterning, application generalization, cost and density issues.

Challenges with resistive scaling, and possible solutions, were another area of discussion. Dielectric improvements, including air gap technology, were discussed as an area needing attention. The panelists concluded that the industry will scale interconnect dimensions, but that yield, reliability, cost and manufacturing challenges still need to be overcome. Specific technology solutions proposed by this expert panel will be published in Semiconductor Engineering Magazine (www.semiengineering.com) over the next few months. You can read the first part of this expert discussion here.