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The Unsung Heroes of CoventorWare
August 4, 2014
Time required for transient simulation of a MEMS gyro with Coventor behavioral modeling approach (Architect3D until 2009 and MEMS+ thereafter)
Modeling as a Foundation for TSensors Acceleration
November 26, 2014

Breakthrough MEMS Models for System and IC Designers

Published by Coventor at September 7, 2014
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  • CoventorMP
  • MEMS
  • TCAD

We just rolled out MEMS+ 5.0 with lots of new capabilities for our users. I discussed some of the new features, support of scanning mirrors in particular, in a previous post. This time I would like to focus on the new capabilities for exporting reduced order models (ROMs) of MEMS devices that system engineers can place in their Simulink schematics and IC designers can place in their circuit schematics.

Before getting into the technical stuff, allow me to provide some motivation. To design the control and signal processing electronics that go around every MEMS device, system engineers usually work in Simulink while circuit designers work in schematic entry tools such as Cadence Virtuoso. There’s a MEMS block in their flow diagram or schematic with an underlying model that captures the coupled electromechanical behavior of the MEMS device. It’s common practice to “hand craft” the MEMS behavioral model, but hand crafted models have many shortcomings: they’re usually over simplified, capturing only one degree of freedom and omitting nonlinear effects. Furthermore, it’s difficult to keep hand crafted models in sync with evolving device designs. All of these shortcomings can be avoided by using ROMs exported from MEMS+ instead of hand-crafted models.

The ROM export capability was first introduced in our MEMS+ 4.0 release as a means to write out Verilog-A models. Verilog-A is the most commonly used hard ware description language (HDL). Nearly every mixed-signal circuit simulator is able to read and simulate models written in Verilog-A. Verilog-A models are basically text files which can be easily exchanged without requiring special software or licensing. The task of exporting Verilog-A from MEMS+ presented us with two development challenges: 1) how could we shrink our sophisticated C++ based model library into a simple text file?; and 2) how could we satisfy our customer’s needs for IP protection? ROM proved to be the solution: it allowed us to take compact “snap shots” of our sophisticated nonlinear multi-physics models, which we write out as text. Since those “snap shots” are essentially abstract mathematical matrices, all geometrical design IP stays protected even if the actual Verilog-A model can be opened and read in any text editor.
Not only has Verilog-A model export proved to be an excellent way to exchange information with in-house engineers or external partners without revealing IP, it has also turned out to be a new milestone in our quest to reduce simulation time. Verilog-A ROMs run up to 100 times faster than our full MEMS+ models in Cadence Virtuoso or MATLAB Simulink. To be sure, there is a price to pay. ROMs are what they are, approximations of their original fully nonlinear masters. Model accuracy is judged differently at different stages of the design process. IC designers are often willing to trade simulation accuracy for speed. In MEMS+ 5.0 we introduce a new set of controls which let users trade accuracy for speed, ranging all the way from a simple linear mass-spring-damper to a sophisticated nonlinear ROM which rivals the original full nonlinear reference in accuracy. In fact, it turned out to be a great strength that MEMS+ allows users to run transient simulations with both the fully non-linear model and the ROM, and compare the results. Imagine doing this with ROMs extracted from standard FEA codes? In fact, we quickly learned how essential it is to have an accurate nonlinear reference when creating a ROM.

As soon as we introduced fast running ROMs in Verilog-A, our customers requested ROMs for MATLAB Simulink as well. I’m proud to say that we added this capability in MEMS+ 5.0! In MEMS+ 5.0 users can decide whether to write out ROMs in Verilog-A or our new MROM file format. MROM files can be loaded into Simulink just like any other MEMS+ schematic file. The corresponding Simulink symbol will be created automatically.

Furthermore, MEMS+ 5.0 includes another world’s first: simulation results from the new MROMs can be viewed and animated in 3D, just like results from full MEMS+ models. With MEMS+ 5.0, users can benefit from the unrivaled simulation speed of ROMs without forgoing the critical insights provided by 3D result visualizations.

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