DAC 2015 is in full swing in San Francisco this week, and Coventor is there again. But this year, we’re also doing a special joint demonstration with Silicon Cloud International. This demonstration combines the power of Coventor’s SEMulator3D Virtual Fabrication platform with broad parallel computing offered by Silicon Cloud to produce a whole new capability that we call “3D Design-Technology Checking” or 3D-DTC for short (not DRC!).

The motivation for 3D-DTC is clear. We hear it loud and clear from the semiconductor industry: 2D DRC alone is not good enough to ensure first-time product yield, especially for early technology adopters. Early 2D DRC decks are immature, incomplete and in the new 3D, multi-patterning era, incomprehensible. This punishes everyone in the ecosystem. PDKs are stuck between designers demanding density and technologists that aren’t finished developing the process. Designers can’t design with these decks, but also can’t have confidence that their designs will yield. The foundry gets squeezed from all sides, and tries to compromise through a process of Design-Technology Co-Optimization (DTCO), but most of this is done through empirical data or guesswork.

SEMulator3D enables process-predictive virtual fabrication of any design in any process flow. This has been shown in many different applications, so I’m not going to waste time on the fundamentals here. Using SEMulator3D’s Automation features, users can easily virtual fabricate hundreds or thousands of models representing process or design variations, and then check them in true 3D space for critical yield criteria. The broad computational resource added by Silicon Cloud allows this to be done across a huge process space in a very short time. This is the answer to the escapes of 2D DRC… 3D-DTC!!!

In the DAC demonstration, a single design construct is analyzed: A pair of semi-isolated M2 lines, connected to dense M1 wiring with a staggered V1 configuration. This design is virtually fabricated in a 10nm-like BEOL technology, complete with Trench-First SADP Mx patterning, LELE Vx patterning and advanced metallization. By varying lithography, deposition and etch processes, we easily see where this design construct is subject to yield-limiting mechanisms. We only used a small portion of the cloud (we had to leave some free for other software demos!), but were able to run 89 virtual DOE wafers through the full process flow and a suite of 3D-DTC rules in just over an hour. And, we got tremendously valuable information about the Design-Technology sensitivities of this structure, such as the points of Minimum Insulator failure (a key reliability metric) and Minimum Metallization failures (a key resistance and reliability metric)… despite being 2D DRC clean!

• In my previous life as an integrator, this would have required ~200 real wafers in the fab (at a cost of ~$1M) over the course of experiments that would take a few months;
• If we had released the rest of the cloud resources on this experiment, it would have completed in 11 minutes!

It’s clear to me that 3D-DTC represents the future of Design-Technology Co-Optimization that’s required for complex designs in advanced technologies. You can see the first cloud-based demonstration of 3D-DTC at DAC right now. The 3D-DTC demonstrations will continue throughout the exhibition at the Silicon Cloud International booth (#3333), so head over to the Moscone Center ASAP!