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In the semiconductor modeling world, no simulation software can do everything. That is, each has its own strengths – process modeling, lithography analysis, and circuit design being a few examples. Semiconductor engineers who perform simulation need to understand the strengths of each of their tools and use them together to take advantage of what each has to offer. Here, we show how SEMulator3D® software can generate meshes compatible with a wide variety of other electronic design and analysis (EDA) tools, and discuss the advantages of using this capability.
In addition to its other capabilities, SEMulator3D can export realistic and silicon-accurate 2D and 3D semiconductor structural meshes. A mesh is a collection of two and/or three-dimensional elements (defined by their points or vertices) that describes the geometry of the structure in question (Figure 1). SEMulator3D users can take advantage of one of its primary strengths – generating highly accurate 3D models – while still working with other software tools that accept a mesh for input. This allows SEMulator3D silicon-accurate 3D structures to be used with other common software tools that cannot generate these structures on their own.
Figure 1. Fin model built with SEMulator3D (top left), visualized SEMulator3D-generated mesh (top right), and close-up of the same mesh (bottom).
In SEMulator3D, there are currently three different types of meshes that can be selected during the mesh export step. Available mesh export types include Delaunay, standard, and simple meshes (Figure 2). There are also different types of mesh file extensions that allow a user to choose how the mesh information is stored in a saved file. The file extension (or format) is dictated by the target software and/or the targeted use. For example, for meshes to be imported into MathWorks® MATLAB® or Simulink®, the user chooses the *.STL file extension when naming the mesh export files. SEMulator3D mesh files are compatible with a wide and diverse range of software tools.
Figure 2. SEMulator3D meshes generated for the model shown in Fig. 1. Left: Delaunay; Center: standard; Right: simple. Cross sections are shown for the Delaunay and standard meshes but the full model is shown for the simple mesh because the volume mesh is not accessible and thus no cross-section view is possible.
In addition to different mesh file types, there are two different mesh structures generated in the mesh export step: a 3D volume mesh and a 2D surface mesh. The volume mesh represents the geometry of the entire 3D structure. The surface mesh represents the geometry on the exterior face of a 3D volume, and will vary based upon how the volume mesh was built. A volume mesh is always generated in SEMulator3D, whether the user saves it or not (the surface mesh must always be saved by the user). The volume mesh is not generated when using the “simple” mesh type.
There are some additional considerations when exporting a mesh using SEMulator3D. Computer memory is an important factor, particularly when meshing a complex and/or large structure. Even with sufficient memory, meshing may take a significant amount of time in any EDA software. Additionally, there may be aspects of the receiving software that should be considered during the mesh export process. Some third-party software has an upper limit on the number of elements in an imported mesh file. There are several parameters that a user can modify in SEMulator3D during the mesh export process to control the exported mesh, such as maximum mesh element size, types of mesh optimization (global vs. local), and the time limit of the mesh optimization process.
In summary, semiconductor engineers can take advantage of SEMulator3D’s ability to generate realistic semiconductor geometries and easily export silicon-accurate 2D and 3D mesh geometry to third-party tools. Exporting meshes in this manner supports the combined use of SEMulator3D best-in-class 3D modeling with a wide variety of other electronic design and analysis software tools.
![Fig. 2. Silicon spin qubit centered in the dotted circle, control and readout signals (M, P, R, T, and Q) are shown in the inset. Simplified schematics of the quantum point contact and corollary circuits are shown. The voltage source is implemented as a digital-to-analog converter at room temperature. (Taken from [6])](https://www.coventor.com/wp-content/uploads/2022/05/Fig.-2.-Silicon-spin-qubit-centered-in-the-dotted-circle-control-and-readout.png)
![Figure 2: Schematic view of standard CMOS including an electro-mechanical switch monolithically integrated into BEOL [2]. Courtesy: University of California, Berkeley](https://www.coventor.com/wp-content/uploads/2022/04/Figure-2-April-2022-MEMS-Blog-for-Coventor-website.png)
