Figure 1 - SEMulator3D® process flow for creating an airgap in a FinFET model. The visibility deposit step creates the airgap by pinching off the airgap at the top. The CMP step is then used to remove the excess nitride. Scale bar is 10nm. The airgap reduces the parasitic capacitance between gate and source/drain. The size of the airgap can be controlled by varying the etch depth, tilt and source sigma of the etching reagents.