Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology co-optimization (DTCO) are widely used techniques that can ensure the successful delivery of both new processes and products in semiconductor manufacturing. In this article, we will discuss how 3D (3 dimensional) DTCO can be used to improve product yield and accelerate product delivery dates in semiconductor manufacturing.
Lithography hotspot detection and mitigation is an excellent application of DTCO. In conventional semiconductor design, numerous techniques are used to improve lithographic resolution such as optical proximity correction (OPC) and phase shifting mask (PSM). Designs are usually signed off for manufacturing after 2 dimensional single-level checks (2D design rule checks (2D DRC)) such as lithography printability and pattern density verification are complete. This design process worked quite well until multiple patterning processes were introduced over the last few years. The complexity of deposition and etching in these new lithography processes have now made it virtually impossible to separate process steps from the design process, and the variability in these complex processes brings further design challenges. Traditional 2D DRC is no longer sufficient, and a more precise 3D DTCO containing process information is now required to achieve early yield using new, more complex patterning processes.
Figure 1 shows an example of this more advanced 3D DTCO modeling process, available in Coventor’s SEMulator3D product. After traditional 2D DRC, process and variation information is fed into the design flow and is used to build an accurate 3D structure in SEMulator3D. This 3D model can be used to verify problem areas or hotspots highlighted during 2D DRC. Some hotspots identified by simple 2D DRC may not be accurate, due to process margin improvements achieved during deposition, etching or other lithography processes that are not reflected in the 2D DRC analysis. Inaccuracies in hotspots identified using 2D DRC can also occur due to 3D geometry which is over guard-banded due to the use of a 2D definition of design rules. However, 2D DRC will sometimes overlook problems areas or hotspots that can only be identified in advance using 3D process modeling. 3D process modeling can highlight issues with 3D minimum insulating distance, contact area, or other yield-limiting problems. The effects of process variability can also be analyzed using 3D process modeling by studying the effect of process variation on the 3D model structure. These studies can identify yield-limiting design issues that can be visualized prior to fabrication using a tool like SEMulator3D. Once hotspots are identified using 3D DTCO, their underlying causes can be mitigated by making changes to the design or through process modifications.
For example, one can evaluate a new OPC algorithm by starting with a new design (or device) layout in the 3D DTCO process (as shown in Figure 2, below). Using design data and a representation of the specific process steps used, the SEMulator3D virtual fab will create a new 3D structure where the impact from hotspots can be visualized and quantified. The ability to visualize and mitigate hotspots prior to fabrication is extremely valuable. Advanced “virtual” modifications to processes in the lithography module might save months of actual fabrication-based testing of a new design. Hotspots can be resolved by applying different etching and deposition techniques “virtually” within SEMulator3D and examining their impacts on known hotspots. By adopting this suggested 3D DTCO flow, the impact of these different processes can be easily quantified, and individual processes can be optimized to mitigate hotspots.
Figure 2 shows a typical process for building a 3D semiconductor “virtual fabrication” model using design, OPC and process data. The OPC contours and hotspot locations are input to the SEMulator3D engine as design data, and combined with a description of the process within SEMulator3D. Together, this data can produce highly-accurate 3D hotspot integrated models. Due to native support for distributed processing, multi-threaded computation and highly advanced modeling techniques in SEMualtor3D, the virtual 3D hot spot models can be constructed quickly and at high resolution using complex process flows over large design areas.
Figure 3 shows an example of different clips with hotspots from a full chip. Using batch processing in SEMulator3D, regions with potential hotspots are reconstructed and visualized in a 2D/3D map. The location of each region in the device is identified in a coordinate structure, with blue marks representing failure points identified on the 3D virtual model during hotspot analysis. Detailed and quantified failure information is collected, summarized and tabulated automatically by SEMulator3D, where each hotspot is identified by its coordinate, parameter status (pass or fail), and quantified parameter value. The short turn-around time possible using this DTCO flow allows designers and process engineers to quickly optimize both their designs and processes.
As semiconductor technology advances, 3D DTCO flow is going to be critical for yield improvement by minimizing systematic, random and parametric defects through the prevention, detection and repair of projected hotspots. Design process technology co-optimization (DTCO) for manufacturability will be a key success factor for companies that wish to succeed in achieving on-time delivery of new semiconductor products.