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  • Exploring the Impact of EUV Resist Thickness on Via Patterning Uniformity using a Litho/Etch Modeling Platform
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April 15, 2020

Exploring the Impact of EUV Resist Thickness on Via Patterning Uniformity using a Litho/Etch Modeling Platform

Published by Benjamin Vincent at March 24, 2020
Categories
  • Coventor Blog
Tags
  • EUV
  • Extreme Ultraviolet lithography
  • Lithography and Patterning

Via patterning at advanced nodes requires extremely low critical dimension (CD) values, typically below 30nm. Controlling these dimensions is a serious challenge, since there are many inherent sources of variation during lithography and etch processing. Coventor personnel, in conjunction with our colleagues from ASML® and imec®, recently looked at the impact of Extreme Ultraviolet lithography (EUV) resist thickness on via patterning CDs. In particular, we looked at Local Critical Dimension Uniformity (LCDU) measured during After Development Inspection (ADI) and After Etch Inspection (AEI). This work was presented during the February 2020 SPIE Advanced Lithography Conference in San Jose, California.

This study was completed without the requirement for any fab-based testing, using the SEMulator3D® virtual fabrication software. A lithography/etch simulation platform was developed by integrating a SEMulator3D analytical model and an optical simulation performed on Hyperlith® software. We simulated a series of 3D resist profiles for a given lithography dose, focus and resist thickness.

Trench profile evolution during Silicon-On-Glass (SOG) / Silicon-On-Carbide (SOC) etch was also modeled for different incoming resist profiles, by calibrating simulation results to existing cross-section data in silicon. This methodology is depicted in Figure 1.

Figure 1: Simulation methodology to measure the impact of lithography and etch parameters on Via LCDU
Fig 1: Simulation methodology to measure the impact of lithography and etch parameters on Via LCDU

The impact of nominal resist thickness on ADI and AEI Via LCDU was determined by running virtual Design of Experiments (DOEs). These DOEs introduced three different sources of variation (resist thickness, dose and focus) in order to generate ADI and AEI CD distributions and to determine their standard deviation.

For each of the nominal resist thicknesses (40, 50 and 60 nm), a virtual DOE was executed assuming uniform Monte Carlo distributions for:

  • Resist thickness with +/- 5% variation range to target
  • Litho dose with +/-10% variation range to target
  • Litho focus with +/- 20 nm variation range to target

The ADI and AEI CDs were automatically measured for each of the 300 simulated variation experiments generated during the study.

Fig 2: Increasing the resist thickness provides a reduction in both ADI and AEI CD standard deviation, if the nominal dose is established to target the same AEI mean CD for each of the three thicknesses
Fig 2: Increasing the resist thickness provides a reduction in both ADI and AEI CD standard deviation, if the nominal dose is established to target the same AEI mean CD for each of the three thicknesses

The initial DOE was executed by establishing the nominal dose for each resist thickness to target the same median CD after development (ADI CD). Figure 2 (left) displays the distribution and the standard deviation of the 100 CDs measured after lithography and after-etch. Note that the median AEI CD is reduced when the resist thickness increases. The resist thickness, however, has little effect on ADI LCDU standard deviation and only causes a slight increase in AEI LCDU standard deviation when the resist thickness is varied from 40 to 60 nm.

A second DOE was then executed using nominal dose compensation in order to target the same median CD after-etch (AEI CD) for the different resist thicknesses. In this case, as reported in Figure 2 (right), the Via CD standard deviation decreases with an increase in resist thickness for both the ADI and AEI cases.

This study highlights a key improvement path for Via patterning LCDU reduction, both after lithography and after etch, by increasing EUV resist thickness. This trend was validated on silicon in the fab by the imec/ASML teams.

Using virtual fabrication technology, we were able to test a large number of experimental EUV resist conditions without the time and cost of actual wafer fabrication. These experimental results would have been impractical to reproduce using silicon data, due to the large number of experimental variations tested.

Interested in learning more?

Download the full whitepaper “Impact of EUV Resist Thickness on Local Critical Dimension Uniformities for <30 nm CD Via Patterning” to learn more about this study.

Download Full Paper

 

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Benjamin Vincent
Benjamin Vincent
Benjamin Vincent is the Worldwide Senior Manager of the semiconductor process and integration (SPI) team at Coventor. He has 15+ years of experience in semiconductor process engineering, including a position at imec (Belgium) from 2008 to 2012 as an epitaxy scientist in the advanced logic area. In 2013, he joined Intel in Santa Clara, CA, working on the development and launch of the first Intel Si photonics products (100G optical transceivers). Dr. Vincent joined Coventor in July 2017, first working for Coventor’s SPI group in Europe performing semiconductor process development and applications engineering. He received his MS Physics and Ph.D. in Material Science from the Institut Polytechnique de Grenoble, in Grenoble, France.

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