Coventor provides a chapter for latest book on MEMS design: System-level Modeling of MEMS.
March 14, 2013Will there ever be a “standard” MEMS process?
September 16, 2013
IBM and Coventor jointly presented a paper at the 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
The paper presents a technology development methodology that relies on 3D virtual fabrication using Coventor’s SEMulator 3D platform to rapidly improve yield by increasing tolerance to multilevel process variation. This methodology has been successfully implemented in the development and yield ramp of high–performance 22nm SOI CMOS technology. Based on virtual metrology, dedicated test site structures were designed and implemented, with electrical results corroborating virtual findings, validating the methodology. This 3D virtual fabrication technique was used to implement a delicate process change, and the same test site structures validated the improved process window yield.
DOWNLOAD the white paper: IBM, Coventor use virtual fabrication at 22nm
![Fig. 2. Silicon spin qubit centered in the dotted circle, control and readout signals (M, P, R, T, and Q) are shown in the inset. Simplified schematics of the quantum point contact and corollary circuits are shown. The voltage source is implemented as a digital-to-analog converter at room temperature. (Taken from [6])](https://www.coventor.com/wp-content/uploads/2022/05/Fig.-2.-Silicon-spin-qubit-centered-in-the-dotted-circle-control-and-readout.png)
![Figure 2: Schematic view of standard CMOS including an electro-mechanical switch monolithically integrated into BEOL [2]. Courtesy: University of California, Berkeley](https://www.coventor.com/wp-content/uploads/2022/04/Figure-2-April-2022-MEMS-Blog-for-Coventor-website.png)
