Figure 1 displays a single cell of a conventional DRAM that consists of 2 Word Lines (WLs), a Bit Line (BL) and 2 Storage Node Contacts (SNC) in Figure 1(a). There are 3 images in the figure. The Saddle Fin is produced during the WL etch step (prior to WL metal deposition) and is located below the cell wordline (Figure 1(b), right center inside a yellow dotted circle). The Saddle Fin structure can be seen in detail by making a vertical cut in the wordline direction (Fig.1(b), right). During device simulation, the Saddle Fin performance can be measured by virtually cropping a transistor and adding ports at the Gate, Source and Drain after an SNC Process (Fig.1(c), showing the gate, source and drain).