Figure 1: A virtual model of a GAA FET showing residual SiGe after the channel release step. Process engineers have to make a trade-off between silicon loss and residual SiGe.(b) Variation in residual SiGe as a function of the channel width and etch lateral ratio. The higher the channel width, the higher the lateral ratio needed to etch away all the SiGe. Channel widths are shown as delta values from the nominal value of 30 nm.