Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog will discuss an efficient technique to develop new process steps faster, with much less effort.
The easiest way to predict a process result is to model its behavior first, and then use the process model on different incoming structures to evaluate the effect of the same process on different starting structures or substrates. A simple model of the incoming structure can be developed using reference data (TEM image) from a known incoming structure. Information about the chemistry and physics of various processes, along with process recipe parameters, can then be fed into a model that emulates process behavior. With this data, an engineer can then model the resulting 3D (simulated) structure if a new process is performed on the incoming structure. If the model mimics actual process behavior accurately, and incoming conditions are well-controlled, the simulation results will not be significantly different from actual fabrication results. The model should be able to accurately predict the outcome (resulting fabricated structure) quite precisely.
In the case of a complicated process with more than one mechanism or behavior, we can even split the complex process up into several steps to develop a more accurate model for that one process. There may be some missing behavior that the model cannot precisely describe, but for many models the result will be sufficient to supply results that are quite useful to a process engineer. Using our incoming structure and the expected process behavior, we can not only predict the results of running the process against the incoming structure, but we can extend our prediction range out of the process window to predict trends. This analysis can be quite useful in looking at potential problems with process variability and yield impact.
We can start process modeling by using a virtual replica of our initial device structures in combination with accurate (predictive) behavioral process models. As an example, Figures 2 and 3 display the results of a sample etch process (behavioral model) applied against 3 slightly different initial device structures. In this case, the process model shows that the after-etch devices, using an identical etch process, differ significantly due to variations in the initial 3D structure. A process engineer can use wafer test data to model a base process condition and base incoming structure, and then look at variations in the structure and process conditions after a series of unit processing steps.
In our example, the process model also displays different curved sidewall shapes for each of the different device structures. This result occurred due to the variation in flux distribution received on the etched surface of each of the structures based upon the different opening sizes of each structure.
Using this virtual process modeling technique, we can obtain defect and failure information for a new device technology. Using our example, we could calculate the amount of over-etch time needed for a device with a smaller opening, locate the failure points of under-etch and over etch for a device with a larger opening, or understand how a smaller pitch might create potential yield problems due to bowing issues with adjacent structures.
Coventor’s SEMulator3D® is a virtual process modeling tool that can perform this type of analysis. Along with the capabilities that have been reviewed, SEMulator3D also has “virtual metrology” capabilities. Virtual metrology tools can be used to make “virtual” measurements at any point in a virtually-generated structure and help quantify or identify threshold values for potential defects. Design and failure ‘rules’ can be constructed using the results obtained from the process models, and statistical analysis can be performed to understand failure probabilities. In addition, SEMulator3D has a built-in “structure search” capability to analyze a 3D model area for process sensitivities or structural violations (including hot spot analysis).
Process modeling is a powerful technique to predict process results quickly and locate potential process issues without wafer-based testing. These process-modeling capabilities are fully-integrated in the SEMulator3D software platform. Once a process model is built in SEMulator3D, any changes to a proposed integration scheme or device design (such as layout or hardmask thickness changes) can be easily visualized and quantified, without the time and expense of wafer testing. The process of building a 3D device using a process model (instead of physical wafers) is called “virtual fabrication”.
Using virtual fabrication in conjunction with calibration cycles, process engineers and integration engineers can easily develop a process and integration model. The accuracy and predictability of any model is dependent on the quality of the input data, but SEMulator3D is able to model a wide range of physical process behavior with great accuracy and can solve highly-advanced process problems. The technology can be used to develop successful processes much faster than conventional “build and test” techniques, with much less effort.