By Mike Hargrove
Most process/device simulation tools are TCAD-based. By this, I mean they share a common platform which connects the process simulator to the device simulator, usually using the same mesh structure. Most all of these TCAD tools are finite-element based, and the 3D final mesh structure is tetrahedral in nature. The mesh structure contains many nodes which define solution points for the numerous complex set of equations required to create the physical structure, in most cases a transistor, and solve for the electrical characteristics of the device. One of the drawbacks of TCAD is the computational time required to arrive at a solution – both process model solution and device electrical solution. A larger modeled area (e.g. multiple transistors and/or an SRAM cell) usually means longer simulation time.
Coventor’s virtual wafer fabrication approach addresses this challenge. Our process modeling platform combines with the statistical device TCAD suite of tools from Gold Standard Simulations, LTD. (GSS) to produce SRAM device-level simulation capability capturing real process-induced statistical variation. The ultimate objective of statistical device modeling is to capture the intrinsic variation of physically relevant process parameters. The combination of Coventor SEMulator3D process modeling capability and GSS statistical TCAD simulator GARAND fulfills this objective.
We recently were able to demonstrate the benefits of this collaboration with GSS using a generic 16nm FinFET SRAM cell. The goal was to model the generic SRAM cell within SEMulator3D and capture Fin profile variations determined by specific Fin-module process variations, e.g. Fin etch process – depth and angle. The process of record (POR) Fin etch module is set to a nominal 100 nm deep with a nominal etch angle of 7o. The Fin-exposing STI recess etch is nominally set to 31nm deep. Each of these process module steps are then varied in a DOE context which results in a statistical variation of final Fin profile.
The major advantage of SEMulator3D over typical TCAD tools is its ability to model large areas, very quickly, thanks to its voxel-based mesh and computational engine. In this GSS/Coventor collaboration, a 16nm FinFET SRAM half-cell is modeled in SEMulator3D, as shown below. The computational time required to model the entire 16nm FinFET POR through MOL in a process-predictive manner is less than one hour. Additional Fin profile variation simulations obviously adds to the total computation time, however, a 5-way by 3-factor (15 total runs) variation study is completed in just a few hours. The SRAM cell design is imported from Coventor’s standard Layout Editor, using industry standard GDSII data format.
SEMulator3D has the capability to output tetrahedral meshes for easy import into standard TCAD tools, as well as uniaxial voxel-based meshes. The tetrahedral mesh output is shown below with the individual pull-up (PU), pull-down (PD), and pass-gate (PG) transistors cropped and output as well for single transistor simulation studies. Advanced modeling capability allows the variation of multiple process parameters, e.g. mandrel spacer width which defines the initial Fin width, to study the effect of Fin profile on individual transistor performance.
The final replacement metal gate (RMG) device cross-section is accurately modeled by a calibrated set of high-k parameter values that realistically represent existing published data.
The PU and PD devices were simulated in the GSS TCAD tool GARAND and the electrical (hole density profile) characteristics for the PU device is shown below. Hole-density as a function of bias condition (the middle figure showing the Fin cross-section) is an important characteristic is optimizing device performance. The figure on the right shows a 3D hole-density contour plot through the middle of the channel from source-to-drain. Note the discrete dopant atoms throughout the body of the device. Additional variation modeling and TCAD simulation are ongoing and will be reported on in the near future.
