Micro Loading and its Impact on Device Performance: A Wiggling Active Area Case in an Advanced DRAM Process

In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1].With transistor sizes approaching the lower limits of physical achievability, manufacturing variability and micro loading effects are becoming increasingly critical DRAM performance (and yield) limiters. The transistor’s AA (active area) dimension and profile are important factors that influence advanced DRAM yield and performance. In this study, we will demonstrate how SEMulator3D can be used to study micro loading and manufacturing variability in an advanced DRAM process that exhibits a wiggling AA profile [2].

A. Wiggling AA and its mechanism

Wiggling AA profiles can be found in almost all commercialized DRAM products produced by leading DRAM manufacturers. The wiggling AA profiles exhibit not only wiggling center lines, but also CD differences in the regions neighboring the cut areas (see Fig. 1) [3,4,5].

Fig. 2 presents a brief illustration of the transistor  fin etch process. During the fin (AA) dry etch process, the sidewall will be passivated by the etch byproduct and exhibit a taper sidewall profile. Since more Si needs to be removed from the region around site A than from the region around site B, more reagent will be consumed, and more byproduct will be generated around site A than around site B (see Fig. 2(b)). Finally, sidewall passivation near site A displays a much more tapered sidewall profile than the region near site B after fin etch (see Fig. 2(c)).   This process creates the wiggling AA profile effect described.

B. Wiggling AA modeling

SEMulator3D provides a novel pseudo-3D approach to pattern dependence modeling based on 2D proximity functions.   By using this pattern dependence modeling technique, we can create a 3D model of a DRAM device and mimic a wiggling AA profile.  Figure 3 presents the layout design, pattern-dependent mask, 3D structure and planar view of a DRAM simulation undertaken in SEMulator3D. Comparing 3(d) with Fig. 1(c), a similar wiggling AA profile is observed, demonstrating that the model properly reflects real Si manufacturing results. Figure 4 displays the AA profile at different fin heights, highlighting that the wiggling is much more severe at the bottom of the structure than at the top of the device.

 

C. Device simulation and analysis

In a DRAM cell with a buried word line, the transistor channel is located near the middle of the fin, where the wiggling profile is more severe than at the fin top (see Fig. 4 (c) and (d)).   Consequently, the final fin CD under the channel will be much larger due to sidewall passivation.

To evaluate the impact of the wiggling AA profile on device performance, sidewall angle splits of 0.1, 2.5, and 5 degrees were modeled in SEMulator3D to mimic varying levels of AA wiggling. A single device was cropped out from a full loop DRAM structure to perform electrical analysis (see Fig. 5(b)). Electrical ports (source, drain, gate, and sub) were assigned in SEMulator3D to collect electrical measurements (see Fig. 5(c)). A built-in drift-diffusion solver in SEMulator3D was then used to calculate the electrical performance changes that could be expected due to different wiggling AA profiles.

Fig. 6 displays off-state leakage current distribution calculated in the fin at various sidewall angles.  Most leakage current was concentrated in the center of the fin (for all sidewall angles), far from the gate metal and not strongly controlled by the gate electrical field. Because of the diminished gate controllability in a fatter fin (at a higher sidewall angle), the leakage current density is much higher in a fat fin than in a thinner fin.

Conclusions

In this study, transistor micro loading effects in an advanced DRAM process were analyzed and modeled using SEMulator3D. The analysis demonstrated that micro loading induced during pattern-dependent etch can cause a wiggling AA profile. This micro loading has a large influence on the device’s electrical performance, especially the off-state leakage which is a key factor in determining the data retention capabilities of the DRAM cells.

 

 

References

1. Lee D, Kim Y, Pekhimenko G, Khan S, Seshadri V, Chang K, Mutlu O. Adaptive-latency DRAM: Optimizing DRAM timing for the common-case. In 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) 2015 Feb 7 (pp. 489-501). IEEE.
2. http://www.coventor.com/products/semulator3d
3. DDR4 SDRAM 1x nm tear down report from TechInsights
4. LPDDR4X SDRAM 1y nm ear down report from TechInsights
5. LPDDR4 SDRAM 1x nm tear down report from TechInsights
6. Fried D, Greiner K, Faken D, Kamon M, Pap A, Patz R, Stock M, Lehto J, Breit S. Predictive modeling of pattern-dependent etch effects in large-area fully integrated 3D virtual fabrication. In 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2014 Sep 9 (pp. 209-212). IEEE.