• Skip to main content
  • LOG IN
  • REGISTER
Coventor_New_LogoCoventor_New_LogoCoventor_New_LogoCoventor_New_Logo
  • COMPANY
    • ABOUT
    • CAREERS
    • PRESS RELEASE
    • PRESS COVERAGE
    • EVENTS
  • PRODUCTS
    • SEMulator3D®
      Semiconductor Process Modeling
    • CoventorMP®
      MEMS Design Automation
      • CoventorWare®
      • MEMS+®
  • SOLUTIONS
    • SEMICONDUCTOR SOLUTIONS
    • MEMS SOLUTIONS
  • RESOURCES
    • CASE STUDIES
    • BLOG
    • VIDEOS
  • CONTACT
  • SUPPORT
Contact Us
✕
  • Home
  • Coventor Blog
  • Mid summer release of SEMulator3D adds more accuracy for deposition & CMP
Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation
July 3, 2014
Semicon West attracts the entire value chain to address 3D chip manufacturing challenges
July 23, 2014

Mid summer release of SEMulator3D adds more accuracy for deposition & CMP

Published by David Fried at July 16, 2014
Categories
  • Coventor Blog
Tags
  • SEMulator3D
Cross-sectional images of 3D models using Visibility-Limited Deposition model.

Figure 1. Cross-sectional images of 3D models using Visibility-Limited Deposition model.

Today we officially released SEMulator3D 2014.100. Typically, I wouldn’t be so excited about a “point release”, but this is clearly the biggest interim software release in recent SEMulator3D memory. We’ve added significant capability to an already industry-leading virtual fabrication platform. Many of the features of recent SEMulator3D releases have been focused on Etch enhancements. To complement these enhancements, we’ve stepped up the predictive accuracy of several other process models in SEMulator3D 2014.100, including Deposition and CMP.

The highlight of this release is a new Visibility-Limited Deposition model. This model dramatically improves the predictive accuracy for directional depositions, like Physical Vapor Deposition (PVD) and other plasma enhanced deposition processes. As with other process models in SEMulator3D, we’ve made this process simple to implement and calibrate using a reduced set of process parameters. The key features of this Visibility-Limited Deposition model are the “Source Sigma”, reflecting the directional distribution of the process, and the “Isotropic Ratio”, reflecting the non-visibility-limited component of the deposition process. This model enables a large variety of processes, with a wide range of results.

Cross-sectional images of 3D models using Visibility-Limited Deposition model.
Figure 1. Cross-sectional images of 3D models using Visibility-Limited Deposition model.

The modeling results above demonstrate the process capability range in 2D cross-sections, from very directional depositions in the top row to more conformal processes in the bottom row. Varying source distributions also exhibit different voiding and void shape during the deposition process. This capability will be used extensively in the modeling of state-of-the-art high-aspect ratio device geometries, including DRAM, 3D NAND Flash, MEMS and scaled FinFET CMOS.

SEMulator3D 2014.100 also includes a new Planarizing Deposition model, to more accurately reflect spin-on processes and flowable depositions. While these processes are meant to deliver a planar result, they inevitably retain some non-planarity due to underlying topography. The new Planarizing Deposition model delivers predictive accuracy for many different materials and processes, with various different planarizing behaviors.

Cross-sectional images of 3D models using Planarizing Deposition model.
Figure 2. Cross-sectional images of 3D models using Planarizing Deposition model.

This model also accounts for deposition processes thinner than the underlying topography, resulting in exposed structures. This capability will be utilized to model several of the novel high-aspect-ratio fill processes as well as many of the innovative patterning film-stacks emerging in a semiconductor process environment still waiting for EUV.

There are several other features in SEMulator3D 2014.100, including a new CMP model that more accurately predicts dishing and over-polish behavior in the presence of complex underlying topography, and modeling performance/accuracy enhancements. We’ve also added a helpful process comparison tool that helps developers keep their flows accurately reflecting the fabrication process.

With this long list of features and enhancements, it’s pretty easy to see why I’m so excited for this interim release. These features answer the needs of our growing customer set, and address new complexities in advanced processes. I can’t wait to spend some time with our customers and exploit these capabilities to accelerate their technology development projects!

Share
David Fried
David Fried
Dr. David M. Fried, is Vice President of Computational Products at Coventor, a Lam Research company, where he is responsible for the company’s strategic direction and implementation of its SEMulator3D virtual fabrication 3D process modeling solution. He leads the execution of technology strategy for technology platforms, partnerships, and external relationships. His expertise touches upon such areas as Silicon-on-Insulator (SOI), FinFETs, memory scaling, strained silicon, and process variability. Fried is a well-respected technologist in the semiconductor industry, with 56 patents to his credit and notable 14-year career with IBM, where he was involved in successive process generations from 65-nanometer and lower. His most recent position was 22nm Chief Technologist for IBM’s Systems and Technology Group. He has Masters and Doctoral degrees in Electrical Engineering from Cornell University.

Related posts

Picture of a young man using virtual reality glasses from the 2018 movie “Ready Player One” from Warner Bros.

An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen

January 18, 2023

An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen


Read more - An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen
Figure 4 displays a single image showing how surface roughness can get transferred to materials etched or deposited later. In this image, the surface roughness has led to scumming, which in turn caused lines to get shorted. The figure shows uneven lines due to surface roughness, with material left behind that crosses two of the lines and creates a short.

Figure 4: Surface roughness can get transferred to materials etched or deposited later. Here, the surface roughness has led to scumming, which in turn caused lines to get shorted.

January 13, 2023

Modeling of Line and Surface Roughness in Semiconductor Processing


Read more - Modeling of Line and Surface Roughness in Semiconductor Processing
Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).

Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).

December 19, 2022

The Other Side of the Wafer: The Latest Developments in Backside Power Delivery


Read more - The Other Side of the Wafer: The Latest Developments in Backside Power Delivery
Figure 1:   3D Gyroscope Model example with simulated pressure contours (left), and ambient cavity pressure vs. Q-factor graph with simulated and measured results (right) (courtesy: Murata)

Figure 1:   3D Gyroscope Model example with simulated pressure contours (left), and ambient cavity pressure vs. Q-factor graph with simulated and measured results (right) (courtesy: Murata)

November 28, 2022

Understanding Q-Factors in Gas Encapsulated MEMS Inertial Sensors


Read more - Understanding Q-Factors in Gas Encapsulated MEMS Inertial Sensors

Comments are closed.

Product Information

  • Product Offerings
  • Technical Support & Training
  • Licensing
  • System Requirements

Resources

  • Blog
  • Case Studies
  • Videos
  • 2018 MEMS Design Contest

Company

  • About
  • Press
  • Partners & Programs
  • Contact
© Copyright Coventor Inc., A Lam Research Company, All Rights Reserved
Privacy Policy • Terms of Use
Contact Us
  • LOG IN
  • REGISTER