• Skip to main content
  • LOG IN
  • REGISTER
Coventor_New_LogoCoventor_New_LogoCoventor_New_LogoCoventor_New_Logo
  • COMPANY
    • ABOUT
    • CAREERS
    • PRESS RELEASE
    • PRESS COVERAGE
    • EVENTS
  • PRODUCTS
    • SEMulator3D®
      Semiconductor Process Modeling
    • CoventorMP®
      MEMS Design Automation
      • CoventorWare®
      • MEMS+®
  • SOLUTIONS
    • SEMICONDUCTOR SOLUTIONS
    • MEMS SOLUTIONS
  • RESOURCES
    • CASE STUDIES
    • BLOG
    • VIDEOS
  • CONTACT
  • SUPPORT
Contact Us
✕
  • Home
  • Coventor Blog
  • How To Build A Better MEMS Microphone
Conference dinner view of the life-size outlines of the Titanic and Olympic main deck’s, illuminated by blue light
Comparing MEMS and the RMS Titanic: Some Thoughts from the IEEE MEMS 2018 Conference
February 2, 2018
Improving Patterning Yield at the 5 nm Semiconductor Node
March 21, 2018

How To Build A Better MEMS Microphone

Published by Chris Welham at February 20, 2018
Categories
  • Coventor Blog
Tags
  • CoventorMP
  • MEMS
  • MEMS Microphone
  • MEMS+
A Section of a MEMS Microphone Model

A Section of a MEMS Microphone Model

A Section of a MEMS Microphone Model
A Section of a MEMS Microphone Model

Here at Coventor, we are seeing a lot of interest in simulating noise, particularly for condenser microphones. With any transducer noise reduction is always a plus, and with microphones there are two specific applications that need low noise. One is where the microphone is positioned away from the sound source, such as in video calling or when using voice commands with tablet computers. The other is where multiple microphones are positioned in an array, to detect the direction of incoming sound or for noise canceling applications.

Noise Sources in MEMS Microphones

All microphones generate noise, in the electronics, the package and the sensing element itself. In a MEMS condenser microphone the noise of the sensing element is dominated by thermal noise (also referred to as Johnson-Nyquist noise) created by the flow resistances of the sound port, back plate perforation holes and diaphragm vent holes. Physically, the origin of the thermal noise is the random motion of the molecules of air associated with these the flow resistances. The molecules of air generate movement of the diaphragm which is converted to an electrical signal by an electronic circuit. In practice, the level of noise generated is closely linked to the sensitivity of the microphone: less noise comes at the expense of a lower sensitivity and vice-versa. For this reason, the Signal to Noise ratio (SNR) provides a good indication of performance. The SNR is the difference in decibels between the noise level and the sensitivity under a 1 kHz, 94 dB SPL (1 Pa) reference signal.

Designing MEMS Microphones

MEMS condenser microphones are quite challenging devices to model. In most cases you have non-linear coupled physics to deal with, and complex geometry in the highly perforated back plate. The conventional approach is to linearize the system and use an equivalent circuit model. This approach works, though it requires a high level of modelling expertise, often to the Ph.D. level, to create and maintain the model. Here’s a thought. Rather than build an equivalent circuit model why not just simulate the SNR directly? All you need is to have is the right mix of elements and simulator to do the job. For those not already using the MEMS+® module of CoventorMP®, hopefully you’ll be interested to know we’ve had this capability for a number of years using our integration with Cadence Spectre®. With the next MEMS+ module of CoventorMP due out in Spring 2018, you will also be able run a noise analysis using the MEMS+ simulator. We are really proud of this new leading edge simulation capability for MEMS device designers.

To understand how our solution works, please take a look at the diagram below. This shows a hybrid condenser microphone model. The membrane and back plate are modeled using our multi‑physics finite elements. Lumped elements are used for the vent hole, back-chamber and the sound port. If you’re only looking at the sensing element (i.e. no attached electronics) you can directly run a simulation in MEMS+ and/or MathWorks MATLAB®.

Diagram showing MEMS+ hybrid model comprising distributed finite elements and lumped elements. All dissipative elements act as thermal noise sources.
Diagram showing MEMS+ hybrid model comprising distributed finite elements and lumped elements. All dissipative elements act as thermal noise sources.

Using either tool, you can predict the sensitivity and noise of any output field. For noise, this could be displacement noise, or more usually capacitance noise. The latter can be easily converted into a voltage noise and then integrated across the audio band with an A-weighting filter. Then, it’s a simple step to combine the noise with the sensitivity to get the SNR value.

Of course, you might want to go a step further and model the electronics with the sensing element of microphone using Cadence Virtuoso®. Here, for example, you can add a constant-charge bias circuit and run the sensitivity and noise analysis in Cadence Spectre. The SNR can be computed using the Cadence Virtuoso Calculator®. Incidentally, you are also only a few clicks (and a few minutes) away from predicting Total Harmonic Distortion (THD) too.

Cadence Virtuoso schematic with ¼ microphone model, displaying calculated sensitivity, noise, SNR and THD
Cadence Virtuoso schematic with ¼ microphone model, displaying calculated sensitivity, noise, SNR and THD

If you would like to know more, please feel free to review our MEMS Microphone Design page or contact us for a demonstration. We’re also keen to hear of any simulation problem that you have – perhaps we can help out?

Share
Chris Welham
Chris Welham
Chris Welham, Ph.D. is the Technical Director of MEMS Applications at Coventor, where he manages Worldwide Application Engineering for Coventor’s MEMS software group. Chris has a BEng in Electronic Engineering and a PhD in Engineering, both from Warwick University. His Ph.D. work was focused on resonant pressure sensors. After obtaining his Ph.D., Chris worked for Druck developing commercial resonant sensors and interface electronics. Chris is based in Coventor's Paris office.

Related posts

Figure 1 displays a single cell of a conventional DRAM that consists of 2 Word Lines (WLs), a Bit Line (BL) and 2 Storage Node Contacts (SNC) in Figure 1(a). There are 3 images in the figure. The Saddle Fin is produced during the WL etch step (prior to WL metal deposition) and is located below the cell wordline (Figure 1(b), right center inside a yellow dotted circle). The Saddle Fin structure can be seen in detail by making a vertical cut in the wordline direction (Fig.1(b), right). During device simulation, the Saddle Fin performance can be measured by virtually cropping a transistor and adding ports at the Gate, Source and Drain after an SNC Process (Fig.1(c), showing the gate, source and drain).
May 30, 2023

Improving DRAM Device Performance Through Saddle Fin Process Optimization


Read more - Improving DRAM Device Performance Through Saddle Fin Process Optimization
Figure 6 (left to right): Different profiles using pattern dependence for the antenna and sharp head shapes. a) Antenna shape with POR flow (b) Antenna profile with a gate CD of 26nm (c) Sharp head profile with a gate CD of 28nm (d) Sharp head profile with an etch.

Figure 6 (left to right): Different profiles using pattern dependence for the antenna and sharp head shapes. a) Antenna shape with POR flow (b) Antenna profile with a gate CD of 26nm (c) Sharp head profile with a gate CD of 28nm (d) Sharp head profile with an etch.

April 13, 2023

The Impact of Metal Gate Recess Profile on Transistor Resistance and Capacitance


Read more - The Impact of Metal Gate Recess Profile on Transistor Resistance and Capacitance
Figure 1a (left) displays the process of performing Physical Vapor Deposition (PVD), including Cu bombardment and filling of voids. Figure 1b (right) displays the process of performing Ion Beam Etch (IBE), including ion beam bombardment, mask shadowing and etch regions.

Fig 1a Physical Vapor Deposition (PVD); Fig 1b Ion Beam Etch (IBE)

March 22, 2023

A Deposition and Etch Technique to Lower Resistance of Semiconductor Metal Lines


Read more - A Deposition and Etch Technique to Lower Resistance of Semiconductor Metal Lines
Left to right: SEMulator3D virtual structures of NON, Low K and Airgap spacers for a DRAM cell, with highlighted SiO2, Polysilicon, Silicon, Si3N4, TIN and W layers

Fig. 1: (a) NON, (b) Low k and (c) Airgap spacer

February 28, 2023

A Comparative Evaluation of DRAM bit-line spacer integration schemes


Read more - A Comparative Evaluation of DRAM bit-line spacer integration schemes

Comments are closed.

Product Information

  • Product Offerings
  • Technical Support & Training
  • Licensing
  • System Requirements

Resources

  • Blog
  • Case Studies
  • Videos
  • 2018 MEMS Design Contest

Company

  • About
  • Press
  • Partners & Programs
  • Contact
© Copyright Coventor Inc., A Lam Research Company, All Rights Reserved
Privacy Policy • Terms of Use
Contact Us
  • LOG IN
  • REGISTER