MEMS Microphones – A Bright Spot among Commoditized Consumer Sensors
March 15, 2017
What drives SADP BEOL variability?
May 17, 2017Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. You will only obtain your final product after a series of etching and deposition steps. So, it is not straightforward for anyone to picture how a given photoresist shape will affect their patterns on chip. They need to analyze all the steps following photolithography to understand how small changes in the photoresist shape will modify their pattern.
This prior February, I gave a presentation on how photoresist shape affects the fin shape and back-end-of-line (BEOL) capacitance in SADP flows at the 2017 SPIE Advanced Lithography conference. In our presentation, entitled “Investigation of 3D Photoresist Profile Effect in Self-Aligned Patterning through Virtual Fabrication”, we used a process modeling platform (SEMulator3D) in some critical use cases to predict final patterns when the starting photoresist shape has sidewall deformations.
One of the cases was fin patterning for FinFETs. Two components of photoresist sidewall profile, taper angle (0° to 14°) and roughness amplitude (0 nm to 10 nm), were varied to create 42 test cases. Each of these photoresist sidewall profile cases was used to pattern a 9-cell, 54-transistor, SRAM array. In order to make sure that these 54 transistors were sufficiently different, line edge roughness (LER) was applied to photoresist lines with 2-nm amplitude and 30-nm correlation length.
For the case of BEOL, LER and sidewall profile was applied on the second metal layer (M2) in a region with two intertwined metal lines. Using SEMulator3D’s built-in capacitance solver, the effects of photoresist shape variation were quantified in electrical performance. In this case, we did not use 54 different sites on a chip. Rather, we varied the randomization of LER by using a different ‘random seed,’ and thus obtained a statistical variation for a given case.
In the fin case, simulations show that the increase in resist sidewall roughness and taper angle leads to a more tapered mandrel, which in turn reduces fin width CD and worsens CD variation. This led to a loss of control on the final fin shape across the wafer.
In the metal interconnect case, the sensitivity to sidewall profile appears to be increased, due to tighter spacing between two neighboring mandrels. Furthermore, capacitance values measured within the virtual fabrication platform highlighted increased variation as the resist sidewall profile is varied. This further supported the conclusion seen in the fin shape case: Increased resist profiles reduced predictability of the final shape obtained by a self-aligned multi-patterning scheme.
If you want to learn more about how small variations in photoresist shape can significantly impact multi-patterning yield, please feel free to download our original SPIE Advanced Lithography paper.
![Fig. 2. Silicon spin qubit centered in the dotted circle, control and readout signals (M, P, R, T, and Q) are shown in the inset. Simplified schematics of the quantum point contact and corollary circuits are shown. The voltage source is implemented as a digital-to-analog converter at room temperature. (Taken from [6])](https://www.coventor.com/wp-content/uploads/2022/05/Fig.-2.-Silicon-spin-qubit-centered-in-the-dotted-circle-control-and-readout.png)
![Figure 2: Schematic view of standard CMOS including an electro-mechanical switch monolithically integrated into BEOL [2]. Courtesy: University of California, Berkeley](https://www.coventor.com/wp-content/uploads/2022/04/Figure-2-April-2022-MEMS-Blog-for-Coventor-website.png)
