Semicon West attracts the entire value chain to address 3D chip manufacturing challenges

Semicon West is one of the iconic conferences in the semiconductor industry and annually attracts the key movers and shakers who are involved with how we are going to keep Moore’s Law moving forward, among other things. It’s known rightfully so, as a ‘big iron’ show with the top manufacturing equipment companies showing off their newest machines for the major steps in the manufacture of semiconductors – wafer processing, assembly packaging and test.

It’s not all about the equipment of course, or even just manufacturing. The show has done a good job of expanding to include a wider ecosystem of companies, products and topics that impact chip design as well. So while the majority of attendees come from companies that produce chips – foundries and IDMs – as well as the supporting production services, Semicon visitors also include the fabless companies who really aren’t in the market for manufacturing equipment.

That underscores a key trend in our industry that is seeing the need for earlier feedback and more insight into the manufacturing process during chip design . And that’s what makes it such a relevant and interesting event for Coventor, and particularly for our innovative SEMulator3D product line. Our ‘virtual fabrication’ platform is increasingly important not just for chip manufacturers, where it is widely used to help reduce build-and-test cycles for new process development and integration, but also for their customers and their suppliers. Yes, SEMulator3D is a valuable tool for the fabless companies and the equipment suppliers, too, as the industry grapples with the challenges of technology complexity at 14nm, 10nm, 7nm and beyond. The semiconductor world is going 3D (FinFETs, NAND Flash) and SEMulator3D is proving to be a key enabler in making that transition happen.

To address the complexity challenges, as well as gnawing issues like the seemingly endless delay in moving to EUV, the industry is collectively looking toward novel approaches, including double, triple, even quadruple patterning to keep Moore’s law going.

So it is important that the fabless companies have a deeper and more accurate understanding of manufacturing related issues. We have seen over the past few years a significant expansion of manufacturing expertise in companies who have never owned or operated a fab. These people are working side by side with the traditional chip designers to understand the impact of design decisions on the ultimate manufacturability of the chip. It goes way beyond the days of simply being handed a set of design rules by your foundry and using that as your primary guide to create a manufacturable design.

These days, chip design companies need the visibility and predictive modeling that a tool like SEMulator3D provides. With it, fabless companies can much more efficiently see whether a design is manufacturable or not, and also quickly find obvious errors or violations.

For the chip manufacturers, the traditional methods of advancing process development – largely through manual methods and relying on years of ‘tribal knowledge’ – are no longer sufficient for the tremendous challenges of today’s advanced semiconductor technologies. Even within the manufacturing world, the lines between the various process steps are starting to blur and becoming increasingly inter-dependent, requiring a solution that provides the “big picture” view at all times. And the equipment suppliers need to understand the detailed nuances of new processes so they can better optimize their machines to keep up with current and future manufacturing trends .

What we saw at Semicon West was a high degree of alignment among several players across the semiconductor value chain about the degree of difficulty and the exploding costs in leading edge process development as well as the strong need for increased collaboration. It also clearly validated the need for a powerful platform like SEMulator3D to address these challenges in a ‘virtual’ way rather than the traditional way of performing costly and time-consuming wafer experiments in the fab.