MEMS+ 4.0: Removing the Barrier between MEMS and ASIC designers
November 4, 2013
Industry experts debate next generation of process development challenges
December 16, 2013Without MEMS today’s smart phones wouldn’t be called “smart”. Be it motion sensing with accelerometers and gyroscopes, noise cancelling with multiple microphones, multi-band radios with tunable RF MEMS capacitors, MEMS are one of the key enablers for completely new or substantially improved functionaloties. This is true not only for smart phones but for many other intelligent devices, in many different application domains. In Europe, we call them “Smart Systems”.
While smart phones and smart systems are becoming coming common place, current industry practices for designing these complex systems are not so smart. According to Salvatore Rinaudo, Industrial and Multi-Segment Sector CAD R&D Director at STMicroelectronics, the lack of a structured design methodology is ‘…the major obstacle to the rapid expansion of smart systems applications.’ Smart system developers use separate design tools for different parts of the system, and most of them do not take the overall system integration into account. Rinaudo made this statement in 2011, but it’s just as relevant today. To address this challenge, key European stake holders have joined forces in two collaborative R&D consortia. One of them is SMAC, which stands for ‘SMArt systems Co-design’, combining expertise from smart systems manufacturers, EDA vendors and academic institutions under the leadership of ST. The other is PARSIMO and focuses on partitioning and modeling of Systems in Package (SIP).
Coventor was pleased to be invited to join these European initiatives on smart system design, specifically to lead the development of tools and methodologies for MEMS-related integration. We were asked to make MEMS design more “integration-aware”. In particular, we were asked to develop solutions for MEMS-package co-design, broad EDA compatibility of MEMS designs, and improvements in simulation speed.
Smart System components addressed by the SMAC consortium
Many years ago, when brain-storming about our next generation MEMS design platform, we envisioned enabling MEMS designers not only to design and optimize their devices, but also to share models with other members in the system design team, starting with the ASIC designers. That vision is now well on the way to reality, embodied in our MEMS+ product suite. Has MEMS design become more “integration-aware” because of our efforts? The answer is definitely “yes”.
One challenge to integrating a MEMS chip into a system is related to its interaction with the package. While the package is meant to protect the MEMS die and interface it to other components, it may also strongly influence its behavior. One of the main reasons is the mismatch of thermal expansion coefficients of the different materials in the package and MEMS substrate. For some devices such as accelerometers, the zero offset caused by thermal effects may overwhelm the actual input signal . Earlier this year we released, as part of MEMS+ 3.0, the ability to incorporate thermally induced substrate deformation in MEMS sensor models. With the addition of damping effects to the existing mechanical and electrostatic modeling capabilities of our MEMS+ suite, it is now possible to perform fully dynamic, nonlinear simulations that take into account the thermal behavior of the package.
While being able to simulate multi-physics effects is a fundamental requirement for MEMS design, it is not sufficient for system design. MEMS models also must be compatible with electronics simulators and simulate very fast in order to allow integration of several electronic components, all without unduly compromising accuracy. MEMS+ models were already compatible with simulators from MathWorks and Cadence, and simulate much faster than conventional finite element models. Could we extend compatibility to other simulators such as HSpice from Synopsys, Mentor Aldo or Silvaco SmartSpice and make the simulations run even faster?
Yes, we accomplished both these goals with the release of MEMS+ 4.0 at the end of October. This release features a new capability to export reduced-order models in standardized Verilog-A format. Model-Order-Reduction (MOR), the process of creating a reduced-order model, is a well-established approach to improving simulation speed. MEMS+ models already had the advantage of a couple orders of magnitude fewer degrees of freedom (unknowns) than conventional finite element models. Performing MOR on the MEMS+ models allows even further reduction in the number of degrees-of-freedom, while preserving accuracy in a selected operational range. Meanwhile, Verilog-A format allows use in the majority of today’s circuit simulators and does not require electronic designers to change the way they work.
Two releases of MEMS+ in 2013 have contributed considerable progress toward the goal of system-aware MEMS design. Looking ahead, our development team is committed to making smart system design even smarter.
![Fig. 2. Silicon spin qubit centered in the dotted circle, control and readout signals (M, P, R, T, and Q) are shown in the inset. Simplified schematics of the quantum point contact and corollary circuits are shown. The voltage source is implemented as a digital-to-analog converter at room temperature. (Taken from [6])](https://www.coventor.com/wp-content/uploads/2022/05/Fig.-2.-Silicon-spin-qubit-centered-in-the-dotted-circle-control-and-readout.png)
![Figure 2: Schematic view of standard CMOS including an electro-mechanical switch monolithically integrated into BEOL [2]. Courtesy: University of California, Berkeley](https://www.coventor.com/wp-content/uploads/2022/04/Figure-2-April-2022-MEMS-Blog-for-Coventor-website.png)
