• Skip to main content
  • LOG IN
  • REGISTER
Coventor_New_LogoCoventor_New_LogoCoventor_New_LogoCoventor_New_Logo
  • COMPANY
    • ABOUT
    • CAREERS
    • PRESS RELEASE
    • PRESS COVERAGE
    • EVENTS
  • PRODUCTS
    • SEMulator3D®
      Semiconductor Process Modeling
    • CoventorMP®
      MEMS Design Automation
      • CoventorWare®
      • MEMS+®
  • SOLUTIONS
    • SEMICONDUCTOR SOLUTIONS
    • MEMS SOLUTIONS
  • RESOURCES
    • CASE STUDIES
    • BLOG
    • VIDEOS
  • CONTACT
  • SUPPORT
Contact Us
✕
  • Home
  • Coventor Blog
  • Toward Smarter Design of Smart Systems
MEMS+ 4.0: Removing the Barrier between MEMS and ASIC designers
November 4, 2013
Coventor CTO David Fried leads a panel of industry experts on a discussion of how to address challenges to continued IC scaling
Industry experts debate next generation of process development challenges
December 16, 2013

Toward Smarter Design of Smart Systems

Published by Gerold Schropfer at December 3, 2013
Categories
  • Coventor Blog
Tags
  • MEMS
  • Technology Reviews
Smart System components addressed by the SMAC consortium

Smart System components addressed by the SMAC consortium

Without MEMS today’s smart phones wouldn’t be called “smart”. Be it motion sensing with accelerometers and gyroscopes, noise cancelling with multiple microphones, multi-band radios with tunable RF MEMS capacitors, MEMS are one of the key enablers for completely new or substantially improved functionaloties. This is true not only for smart phones but for many other intelligent devices, in many different application domains. In Europe, we call them “Smart Systems”.

While smart phones and smart systems are becoming coming common place, current industry practices for designing these complex systems are not so smart. According to Salvatore Rinaudo, Industrial and Multi-Segment Sector CAD R&D Director at STMicroelectronics, the lack of a structured design methodology is ‘…the major obstacle to the rapid expansion of smart systems applications.’ Smart system developers use separate design tools for different parts of the system, and most of them do not take the overall system integration into account. Rinaudo made this statement in 2011, but it’s just as relevant today. To address this challenge, key European stake holders have joined forces in two collaborative R&D consortia. One of them is SMAC, which stands for ‘SMArt systems Co-design’, combining expertise from smart systems manufacturers, EDA vendors and academic institutions under the leadership of ST. The other is PARSIMO and focuses on partitioning and modeling of Systems in Package (SIP).

Coventor was pleased to be invited to join these European initiatives on smart system design, specifically to lead the development of tools and methodologies for MEMS-related integration. We were asked to make MEMS design more “integration-aware”. In particular, we were asked to develop solutions for MEMS-package co-design, broad EDA compatibility of MEMS designs, and improvements in simulation speed.

Smart System components addressed by the SMAC consortium
Smart System components addressed by the SMAC consortium

Smart System components addressed by the SMAC consortium

Many years ago, when brain-storming about our next generation MEMS design platform, we envisioned enabling MEMS designers not only to design and optimize their devices, but also to share models with other members in the system design team, starting with the ASIC designers. That vision is now well on the way to reality, embodied in our MEMS+ product suite. Has MEMS design become more “integration-aware” because of our efforts? The answer is definitely “yes”.

One challenge to integrating a MEMS chip into a system is related to its interaction with the package. While the package is meant to protect the MEMS die and interface it to other components, it may also strongly influence its behavior. One of the main reasons is the mismatch of thermal expansion coefficients of the different materials in the package and MEMS substrate. For some devices such as accelerometers, the zero offset caused by thermal effects may overwhelm the actual input signal . Earlier this year we released, as part of MEMS+ 3.0, the ability to incorporate thermally induced substrate deformation in MEMS sensor models. With the addition of damping effects to the existing mechanical and electrostatic modeling capabilities of our MEMS+ suite, it is now possible to perform fully dynamic, nonlinear simulations that take into account the thermal behavior of the package.

While being able to simulate multi-physics effects is a fundamental requirement for MEMS design, it is not sufficient for system design. MEMS models also must be compatible with electronics simulators and simulate very fast in order to allow integration of several electronic components, all without unduly compromising accuracy. MEMS+ models were already compatible with simulators from MathWorks and Cadence, and simulate much faster than conventional finite element models. Could we extend compatibility to other simulators such as HSpice from Synopsys, Mentor Aldo or Silvaco SmartSpice and make the simulations run even faster?

Yes, we accomplished both these goals with the release of MEMS+ 4.0 at the end of October. This release features a new capability to export reduced-order models in standardized Verilog-A format. Model-Order-Reduction (MOR), the process of creating a reduced-order model, is a well-established approach to improving simulation speed. MEMS+ models already had the advantage of a couple orders of magnitude fewer degrees of freedom (unknowns) than conventional finite element models. Performing MOR on the MEMS+ models allows even further reduction in the number of degrees-of-freedom, while preserving accuracy in a selected operational range. Meanwhile, Verilog-A format allows use in the majority of today’s circuit simulators and does not require electronic designers to change the way they work.

Two releases of MEMS+ in 2013 have contributed considerable progress toward the goal of system-aware MEMS design. Looking ahead, our development team is committed to making smart system design even smarter.

Share
Gerold Schropfer
Gerold Schropfer
Dr. Gerold Schröpfer is Technical Director for Europe and for the MEMS business operations worldwide. For the last ten years, Gerold has been responsible for overseeing Coventor’s European MEMS and semiconductor business activities, including the management of R&D programs, industrial and academic partnerships, and external business relationships. Dr. Schröpfer has more than 20 years of relevant experience in MEMS and semiconductor design, process development and EDA product development. Prior to his current position at Coventor, Gerold carried out pioneering work in the design and development of inertial, tire pressure and magnetic sensors at Sensitec and SensoNor (Infineon). Dr. Schröpfer holds a PhD in engineering science from the University of Neuchâtel (Switzerland) and Franche-Comté (France), as well as a degree in physics from the University of Giessen (Germany).

Related posts

Picture of a young man using virtual reality glasses from the 2018 movie “Ready Player One” from Warner Bros.

An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen

January 18, 2023

An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen


Read more - An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen
Figure 4 displays a single image showing how surface roughness can get transferred to materials etched or deposited later. In this image, the surface roughness has led to scumming, which in turn caused lines to get shorted. The figure shows uneven lines due to surface roughness, with material left behind that crosses two of the lines and creates a short.

Figure 4: Surface roughness can get transferred to materials etched or deposited later. Here, the surface roughness has led to scumming, which in turn caused lines to get shorted.

January 13, 2023

Modeling of Line and Surface Roughness in Semiconductor Processing


Read more - Modeling of Line and Surface Roughness in Semiconductor Processing
Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).

Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).

December 19, 2022

The Other Side of the Wafer: The Latest Developments in Backside Power Delivery


Read more - The Other Side of the Wafer: The Latest Developments in Backside Power Delivery
Figure 1:   3D Gyroscope Model example with simulated pressure contours (left), and ambient cavity pressure vs. Q-factor graph with simulated and measured results (right) (courtesy: Murata)

Figure 1:   3D Gyroscope Model example with simulated pressure contours (left), and ambient cavity pressure vs. Q-factor graph with simulated and measured results (right) (courtesy: Murata)

November 28, 2022

Understanding Q-Factors in Gas Encapsulated MEMS Inertial Sensors


Read more - Understanding Q-Factors in Gas Encapsulated MEMS Inertial Sensors

Comments are closed.

Product Information

  • Product Offerings
  • Technical Support & Training
  • Licensing
  • System Requirements

Resources

  • Blog
  • Case Studies
  • Videos
  • 2018 MEMS Design Contest

Company

  • About
  • Press
  • Partners & Programs
  • Contact
© Copyright Coventor Inc., A Lam Research Company, All Rights Reserved
Privacy Policy • Terms of Use
Contact Us
  • LOG IN
  • REGISTER