Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators that mimic fab unit processes can now be used to model these complex interactions. They can also help process engineers identify important process and/or design parameters that drive certain critical targets such as CDs, yield limiting spacing, 3D design rule violations, resistance/capacitance, and other process and design issues. The number of possible parameters that affect device performance and yield can be quite large, so statistical analysis can provide useful insight and help identify critical performance parameters. Coventor’s SEMulator3D virtual fabrication (or process simulation) platform contains an analytics module for conducting virtual design-of-experiments and statistical analysis. I would like to use an example of a 14nm FinFET process flow in SEMulator3D to identify important process parameters that drive fin top CD, which is a key metric for transistor performance.
In this example, fin patterning flow based on 14nm FinFET technology is being used. The actual process steps are shown in our animated illustration (see Figure 1). Key steps include self-aligned double patterning (SADP) fin definition, fin cut, and STI polish and recess. The final fin top CD is measured in SEMulator3D using virtual metrology and is the key parameter of interest in this study. The nominal fin top CD is about 9.6nm. In this study, we will determine which process parameter(s) most significantly impact fin top CD.
How would we find the answer to this question using SEMulator3D?
We have now completed the screening DOE and identified the most important process parameters that modulate fin top CD. To further explore the process window and variability impact for these most significant parameters, we could repeat the regression using either a Full Factorial or Monte Carlo statistical design method.
The whole process of designing, executing and analyzing this fin top CD screening DOE took less than one hour, without running a single wafer through the fab! We were able to determine the relevant process parameters, such as fin spacer oxide thickness, that most significantly impact fin top CD. Using these results, we would now concentrate our efforts on controlling these parameters by setting inline measurement and metrology specifications, or we could focus on process controls that would reduce variation in the critical parameters. The analytics capability of SEMulator3D provides deep insight into process variability and can be used to improve yield and performance of FinFET and other advanced semiconductor devices.
For further examples of the predictive value of SEMulator3D for FEOL process integration, request a copy of the white paper “FinFET Front-End-of-Line (FEOL) Process Integration“.