Using a Virtual DOE to Predict Process Windows and Device Performance of Advanced FinFET Technology

Introduction

With continuing FinFET device process scaling, micro loading control becomes increasingly important due to its significant impact on yield and device performance [1-2]. Micro-loading occurs when the local etch rate on a wafer is dependent upon existing feature sizes and local pattern density. Unintended features or profiles created by the etch process can negatively impact device yield and performance. As an example, dummy poly profiles resulting from poly corner etch residue can change  FinFET structure profiles, and directly impact FinFET gate length and electrical performance. The impact of poly corner residue on yield and device performance, including what residue size is acceptable, can be predicted in advance using SEMulator3D^®. [3].

Poly Corner Residue Modeling and Process Window Checks for FinFET devices

Poly corner residue can create metal gate protrusions at the fin cross gate area.  These protrusions can be found at many different FinFET nodes, and poly corner residue is commonly formed during the poly etch process [4-7].

Figure 1: Fabricated 3D corner residue and its profile at different elevations.

A 5 nm virtual process model using an SRAM111 structure was built in SEMulator3D to study poly etch residue behavior. In this simulated poly etch process, pattern dependence etch was used in SEMulator3D to simulate a poly residue profile. Figure 1 displays the computer-generated poly residue structure (left). The poly profiles at different elevations (fin top, middle and bottom) are shown on the right-hand side of Figure 1.

How large of a poly corner etch residue is acceptable before a structural hard failure occurs in this simulated device? We investigated this question by testing 100 combinations of residue widths and heights in a virtual DOE (design of experiments).  We measured the number of nets during virtual manufacturing, as a metric to understand the number of epitaxial to poly shorts (or failures) in the device. The number of nets will be less than 3 if the residue is too large and creates an epi to poly short. Fig. 2 displays a contour map containing the number of nets compared to the residue widths and heights. The green area displays proper (non-failing) device structures with 3 nets. Considering the potential manufacturing variability of both residue width and height (potentially 1.5 nm and 5 nm respectively), a “safe” residue window can be found on the left-hand side of the blue dotted line.

Figure 2: Contour map containing the number of nets compared to the residue width and height

Impact of Poly Corner Residue on FinFET Device Performance

Using an acceptable poly residue (with no hard failures), we then simulated the device performance. The results indicated that a larger residue can actually benefit the on-state drive current, off-state leakage, subthreshold swing and DIBL. It can boost device performance with higher on-current (108%) and lower off-state leakage (50%), compared with an ideal structure that had no residue. To further understand the mechanism of this device performance boost, we investigated the on-state and the off-state current distribution at the fin bottom when a larger residue was present (See Figure 3).

During the on-state, the channel length becomes larger when the poly residue is present. The residue covers part of the access area between the source/drain and the gate. Series resistance consequently is smaller, leading to a larger drive current. During the off-state, most of the fin area between the source and the drain can be controlled by the gate. Consequently, the resistance between the source and drain is higher when a poly residue is present and provides lower off-state leakage.

Figure 3: On/off-state current distribution at fin bottom (top figures: no residue; bottom figure: with residue).

Conclusion

In this paper, we used Coventor SEMulator3D to study process windows and the impact of poly corner etch residue on device performance in a 5 nm FinFET process. This study helped us gain a greater understanding of acceptable process windows and associated device performance at different poly residue dimensions. Our study demonstrated that instead of completely minimizing poly corner residue, poly residue size control can be implemented to gain device performance and concurrently maximize yield.

References

1. G. E. Moore, Electronics Magazine, vol. 38, no. 8, pp. 114-117, Apr 1965.
2. B. D. Gaynor et al, IEEE Transactions on Electron Devices, vol. 61, no. 8, pp. 2738-2744, Aug. 2014.
3. http://www.coventor.com/products/semulator3d
4. TechInsights TSMC 12FFN FinFET teardown report.
5. TechInsights TSMC 10FF FinFET teardown report.
6. TechInsights SAMSUNG 10nm FinFET teardown report.
7. TechInsights TSMC 7FF FinFET teardown report.