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Improving SAQP Patterning Yield using Virtual Fabrication and Advanced Process Control

Published by Benjamin Vincent at March 21, 2019
Categories
  • Coventor Blog
Tags
  • DTCO (Design Technology Co-Optimization)
  • Lithography and Patterning
  • SEMulator3D
Composite of Virtual SAQP Model with Actual Si Cross-Section Data (animation)

Figure 1: Composite of Virtual SAQP Model with Actual Si Cross-Section Data (animation)

Advanced logic scaling has created some difficult technical challenges,  including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) line patterning with a 16 nm half-pitch for their 7nm node (equivalent to a 5nm foundry node). Self-Aligned Quadruple Patterning (SAQP) was investigated as an alternative path to Extreme Ultra-Violet (EUV) lithography for this line patterning application.  At the 2019 SPIE Advanced Lithography conference, Coventor personnel demonstrated how virtual process modeling (combined with advanced process control) could provide enhanced patterning yield and enable SAQP patterning at this tight pitch (See Complete White Paper). A summary of the team’s methodology and results are included below.

Composite of Virtual SAQP Model with Actual Si Cross-Section Data (animation)
Figure 1: Composite of Virtual SAQP Model with Actual Si Cross-Section Data (animation)

1. SAQP Process Model Calibration

First, to determine a precise and realistic yield forecast for the SAQP process, a virtual model of the fabrication process was built using SEMulator3D®.   This model was used to study the impact of process fabrication variations on geometric evolution during patterning. Actual hardware data was used to calibrate the model, by including data from numerous Si cross-sections taken at different critical steps of the process flow.  A comparison of the virtual model results and the actual Si cross-sections is shown in Figure 1.

2. Process Variation Analysis and Yield Forecast using Virtual DOE

After calibration was complete, the model was used to execute a virtual Design of Experiments (DOE) study. Two hundred simulations were executed using different Mandrel Critical Dimensions, along with varying Spacer1 and Spacer2 thicknesses (SAQP critical process parameters).  Virtual metrology within SEMulator3D was utilized to measure Critical Dimensions (CDs) of all patterned trenches and the trench spacing.   The Coventor team established success criteria for all trench/line CDs at 16nm +/- 10%.   Under nominal process conditions, they concluded that a 9% patterning failure rate would occur (when looking at acceptable lithography CD and deposition thickness variations).

3. Process Retargeting and Yield Enhancement

The team then introduced a novel concept for eliminating the 9% inherent failure rate, re-targeting Spacer1 and Spacer2 thicknesses based on earlier Mandrel Critical Dimension measurements. The retargeting was constrained by running iterative virtual DOEs until patterning yield was optimized. They executed a second 200 run DOE using this process re-targeting. Figure 2 depicts the final distribution of line and trench CDs obtained under the nominal DOE (left side) and the newly re-targeted DOE (right side). Two trench types (TrenchCore and TrenchGap, corresponding to trenches located within and between the printed mandrels, respectively) show a dramatic improvement in standard deviation distribution. The retargeting improved patterning up to a yield of 99.43%.

Comparison of SAQP Patterning Yield, before and after re-targeting
Figure 2: Comparison of SAQP Patterning Yield, before and after re-targeting

Conclusion

Virtual Fabrication was used to forecast a minimum inherent 9% failure rate for an existing SAQP process targeting 16nm +/- 10% half-pitch. Process retargeting, utilizing a combination of virtual fabrication and Advanced Process Control, was shown to reduce this inherent failure rate to below 1%. To learn more about this topic, please Download the Complete White Paper.

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Benjamin Vincent
Benjamin Vincent
Benjamin Vincent is the Worldwide Senior Manager of the semiconductor process and integration (SPI) team at Coventor. He has 15+ years of experience in semiconductor process engineering, including a position at imec (Belgium) from 2008 to 2012 as an epitaxy scientist in the advanced logic area. In 2013, he joined Intel in Santa Clara, CA, working on the development and launch of the first Intel Si photonics products (100G optical transceivers). Dr. Vincent joined Coventor in July 2017, first working for Coventor’s SPI group in Europe performing semiconductor process development and applications engineering. He received his MS Physics and Ph.D. in Material Science from the Institut Polytechnique de Grenoble, in Grenoble, France.

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