By: Michael Hargrove, Semiconductor Process & Integration Engineer
Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies. For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.
In SADP, not all metal lines are defined in the same way. Some metal lines are defined by lithography patterning, while other metal lines are defined by a combination of lithography patterning and spacer deposition and etch. With a focus on SADP as the present day process of choice for BEOL multi-patterning, I’d like to discuss the variability components of spacer-based deposition and etch, and more specifically spacer-based pitch multiplication techniques.
A typical SADP process flow can be seen in Fig. 1(a). The flow starts with a mandrel definition of a specific critical dimension (CD) and a defined pitch. Mandrel CD will ultimately control the critical dimensions of the metal lines. A spacer material, typically oxide, is deposited and etched to form sidewall spacers. These sidewall spacers open the mandrels for ultimate removal and form a mask used to create the etch pattern. The spacers, along with the mandrel opening, define the ultimate dimensions and positions of the metal lines and trenches.
Virtual fabrication is a computerized technique to perform predictive, three dimensional modeling of semiconductor fabrication processes. SEMulator3D™ is a virtual fabrication solution that can model process variability under complex patterning schemes and process flows. In order to study the impact of spacer-based pitch multiplication process variability on BEOL and ultimately RC performance, we used SEMulator3D to model a typical SADP process flow (Fig. 1(b)). The SEMulator3D software platform enables modeling of both the process flow as well as parasitic resistance and capacitance of the metal lines.
In our model, we varied mandrel lithography definition, as well as spacer deposition and etch, to determine the effect on BEOL and device performance. Our results indicate that variations in these critical process parameters have a significant impact on RC and device performance.
Mandrel definition, along with spacer deposition and final spacer CD, control the characteristics of the metal lines during fabrication. Fig. 1(b) shows the final 3D structure of three parallel metal lines where the outer two lines are defined by the mandrel and the inner line is spacer-defined. For the nominal process, all three metal line CDs are equal. Fig. 2 shows the relationship between mandrel lithography variation and the resulting mandrel CD. Variation in mandrel lithography definition can result in fairly large mandrel CD variation, which can then translate into final mandrel defined metal CD variation (Fig. 3).
Variation in spacer deposition thickness and etch can also generate final spacer CD variability since it controls subsequent trench etch for final metal fill. Variation in both mandrel and spacer definition can combine and result in differences in both the mandrel defined metal CD and spacer defined metal CD, as shown in Fig. 4.
The final metal cross-section CD of our three metal lines at maximum process variation is shown in Fig. 5. Variation in both mandrel and spacer definition creates significant CD deltas between the middle and outer metal lines, which in turn has significant impact on RC performance associated with BEOL parasitics.
Spacer-based, pitch multiplication techniques are currently being used to meet BEOL patterning demands at the 7nm technology node and beyond. In this study, we used virtual fabrication technology to model spacer-based, pitch multiplication process variability and understand the effect of this variability on BEOL and RC performance. Our results indicate that spacer-based, pitch multiplication process variability must be controlled to avoid metal line defects due to variations in mandrel-defined and spacer-defined processes.
For further examples of the predictive value of SEMulator3D for BEOL process integration, request a copy of the white paper “Back End of Line (BEOL) Patterning”.
 T. Huynh-Bao, et al, IEEE Transactions on VLSI Systems, Vol. 25, No. 5, 2017.