When will we get 3D NAND Flash Memory???

Dr. David M. Fried – CTO-Semiconductor

It’s about time for 3D NAND Flash, the agreed-upon “future of memory technology” to stop being the future and start being the present. The concepts all make sense. DRAM scaling is getting more and more difficult, and the speed difference between DRAM and NVRAM (Flash) has closed to some extent. Flash technologies have been using finer geometries than other semiconductor technologies for several 2D nodes, and now they’re running out of steam. So, with these apparently obvious trends, and several massive corporations applying a decade of their research and development efforts to the problem, why are these technologies not in the mainstream yet?

Because 3D is difficult. Really, really difficult.

We’ve been hearing about these technologies for a while. It seemed Toshiba was getting pretty close with BiCS (Bit Cost Scalable), and then even closer with Pipe-BiCS, a denser version of the technology that was potentially easier to fabricate. Samsung joined the discussion with TCAT (Terabit Cell Array Transistor), which seemed to have retention advantages. Samsung recently announced shipping some samples of their V-NAND). At IEDM 2011 and 2012, SK Hynix showed their DC-SF (Dual Control-gate, Surround Floating-gate), and seemed closer than ever to production. Other research institutions and manufacturers have produced similar announcements and publications.

These technologies all fundamentally rely on the concept of building up a multi-layer stack, and then etching small holes all the way through that stack. Thin films have been done for generations, and deep holes have too (trench and stacked-capacitor DRAM). But this combination of stacks 16, 32 or 64 layers high and holes with super-high aspect ratios is incredibly challenging to semiconductor equipment manufacturers and etch process engineers. The challenges continue. Since each of those layers will serve as a control gate along the vertical bitline, there’s a significant amount of process conducted IN THAT DEEP HOLE. Now, this is where the technology goes off the deep-end. In DRAM, the processes to form the capacitor and fill the trenches are complex, but they pale in comparison with what is done in these holes. Multiple etches, oxidations, film depositions, recesses and strips all need to be carefully controlled inside a tiny deep hole. The number of experimental wafers that could be wasted on this module alone boggles my mind. If this wasn’t enough, there’s a crazy stair-case etch process to gain access to the control gates, and then an MOL (Middle-of-Line) that requires contacts to be formed at many different heights. Without significant advances in process design methodologies, such as virtual fabrication, the development of these integrated technologies will continue to be time consuming and experimentally expensive.

An additional aspect that might be at the heart of the delay in 3D NAND Flash is defectivity. The semiconductor industry has decades of experience dealing with defects in fabrication. In order to provide cost-competitive yield in a new generation, fabrication tools are held to the requirement of releasing half the defects at half the defect size relative to the prior generation. New tools with new filters with new cleaning procedures emerge every generation to manage this. But 3D structures put an additional spin on this problem. Imagine this: if a 100ft meteor (defect) strikes a dense residential area of ranch-style homes (2D), the damage is limited to one or two homes. However, if that same meteor strikes an area of densely packed multi-floor apartment buildings (3D), far more people end up displaced. The impact of a defect landing on a wafer is much more dramatic in 3D in terms of “bits killed”. Also, these complex multi-layer-stack integrated memory process flows result in elaborate defect-evolutions. Depending on when in the process a defect lands on the wafer, the results can be dramatically different. Understanding how these defects evolve through the process, isolating them, localizing them and accounting for them in terms of redundancy and yield optimization will unlock the keys to volume manufacturing.

A new class of automation tools that enable early analysis and modeling capabilities, such as Coventor’s SEMulator3D, are emerging to provide the accuracy and efficiency required to significantly reduce the time and costs of the traditional approach for semiconductor technology development. IBM recently published a paper at SISPAD 2013 detailing use of this virtual fabrication methodology to successfully accelerate the production ramp for its 22nm SOI process. The same principles are now being applied to NAND Flash process development. Without these tools, it could be another year or two before we get to use 3D NAND Flash and billions of dollars in additional technology development costs.

This entry was posted in Coventor Blog. Bookmark the permalink.

Comments are closed.