Coventor Blog

Advanced 3D Design Technology Co-Optimization for Manufacturability

By: Yu De Chen, Jacky Huang, Dalong Zhao, Jiangjiang (Jimmy) Gu, Joseph Ervin

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. It is a continuous challenge to meet targets of both yield and cost, due to new device structures and the increasing complexity of process innovations introduced to achieve improved product performance at each technology node. Design for manufacturability (DFM) and design technology co-optimization (DTCO) are widely used to ensure successful delivery of both new processes and products in semiconductor manufacturing. In this paper, we develop a new 3D DTCO model which combines 3D structure optimization and electrical analysis. We discuss how this 3D DTCO model can be used to improve product yield and accelerate product delivery timelines in semiconductor manufacturing. read more…

The Challenge of Modeling the Interaction between MEMS Inertial Sensors and their Packaging

By: Arnaud Parent

Simulation of Thermal Effects on MEMS Performances

MEMS inertial sensors, such as Accelerometers and Gyroscopes, have been commercially successful in the consumer marketplace, where reduced size and cost are more important than accuracy. These sensors are classified as commercial grade products, even though they are typically used in consumer applications. Today, MEMS inertial sensors are knocking on the door of tactical grade applications, where the requirements for accuracy are much more demanding. MEMS products may one day enter the navigation grade application space, where accuracy demands are even more stringent. To meet the enhanced accuracy and performance requirements of tactical and navigation grade inertial sensors, MEMS designers must not only consider the transducer itself but the interaction of the product with its surrounding environment (starting with the packaging). At Coventor, we have a new simulation platform that can be used to create a compact model of MEMS transducers along with their packaging, providing a method to efficiently study the overall behavior of MEMS inertial sensors. read more…

Improving Patterning Yield at the 5 nm Semiconductor Node

By:  Benjamin Vincent, Ph.D., Staff Engineer, Semiconductor Process & Integration

Engineering decisions are always data-driven.  As scientists, we only believe in facts and not in intuition or feelings.

At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconductor manufacturing can provide facts that engineers can use to make immediate and accurate decisions, such as how they might correct any excursion or yield drift. Data exists, so life is (kind of…) easy! read more…

Tagged , , , , , , , , , , ,

How To Build A Better MEMS Microphone

By: Chris Welham, Senior Manager, MEMS Applications Engineering

A Section of a MEMS Microphone Model

Overview

Here at Coventor, we are seeing a lot of interest in simulating noise, particularly for condenser microphones. With any transducer noise reduction is always a plus, and with microphones there are two specific applications that need low noise. One is where the microphone is positioned away from the sound source, such as in video calling or when using voice commands with tablet computers. The other is where multiple microphones are positioned in an array, to detect the direction of incoming sound or for noise canceling applications. read more…

Tagged , , , , , , , , ,

Comparing MEMS and the RMS Titanic: Some Thoughts from the IEEE MEMS 2018 Conference

By: Chris Welham, Sr. Manager, MEMS Applications Engineering

Conference dinner view of the life-size outlines of the Titanic and Olympic main deck’s, illuminated by blue light

How are MEMS and Large Ships Alike?

MEMS 2018 was held in Belfast, Northern Ireland this year, on the site where the RMS Titanic was built. On exhibit was the SS Nomadic, a tender used to transfer mail and passengers to the RMS Titanic and her sister ship RMS Olympic. Passing by the SS Nomadic on the way to the conference dinner, I noticed the riveted plates from which the tender was built. These riveted plates reminded me of the finite element plate models used in the MEMS+ module of CoventorMP, which can also be joined to other elements using “connectors” or “nodes” rather than rivets. read more…

Future Outlook: The Advantages of Fully Depleted Silicon on Insulator (FD-SOI) Technology

By: Michael Hargrove, SP&I Engineer

If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening panel discussion. At that panel discussion, there were many advocates for SOI, as well as many naysayers. I didn’t really think more about SOI technology until the mid-nineties, when I was sitting in a meeting where the first SOI device data was being presented in the hallowed halls of IBM. The data was incredibly scattered and my thinking was “this technology is going nowhere!” The purported performance advantage was stated to be ~35%, simply due to the capacitance reduction (no longer did the bottom junction capacitance play a role) and the speed advantages of stacked devices in a NAND circuit. It all sounded great, but in the mid-nineties, the data simply didn’t support it. Nonetheless, the SOI advocates pursued their beloved technology, and the rest is history. SOI technology has been part of IBM’s main stream high-performance technology base through the 14nm node, including FinFETs on SOI. read more…

What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology.  The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes.  Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.

The Next 5 Years of Semiconductor Technology

L-R: Ed Sperling (moderator), Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt

read more…

Tagged , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

Delivering the Next 5 Years of Semiconductor Technology

New, advanced semiconductor processing and architectural technologies take years to perfect and put into production. In the meantime, semiconductor customers continue to demand faster, smaller and higher functioning devices. Semiconductor manufacturers need to decide whether (and when) to jump to the next generation of devices and production technologies, weighing the risk and benefit of bringing the next processing and architecture technologies to market. read more…