By MARK LAPEDUS
As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm.
Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-popping $1 billion. In addition, there are also several uncertainties at 3nm that could change everything overnight.
That hasn’t sidelined anyone yet, however. Samsung and GlobalFoundries separately announced plans to develop a new transistor technology called a nanosheet FET, with so-called variable widths at 3nm. Samsung, for one, hopes to deliver a PDK (version .01) by 2019, with plans to move into production by 2021. Meanwhile, TSMC is exploring nanosheet FETs and a related technology, nanowire FETs, at 3nm, but it has not announced its final plans. Intel, meanwhile, isn’t talking about its plans.
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By Paula Doe
The fast-maturing hardware and software that are enabling practical applications of equipment intelligence and machine learning mean disruptive change for microelectronics manufacturing. But first comes the basic work of building the basic infrastructure, figuring out IP separation, and learning to solve physical problems in the digital world.
Just how much can the semiconductor industry leverage industrial IoT practices from other industries? Common wisdom may be that industrial software solutions aren’t well suited to the IC sector’s complex needs. But GE Digital enterprise account executive Luke Smaul, currently working with Intel, argues that semiconductor fabs and toolmakers are dealing with similar issues as GE did when it first started working with Delta Airlines to monitor the GE engines on Delta planes. Smaul will speak at SEMICON West about GE’s work with Intel over the past few years and, in particular, how its solution for cloud security and IP separation can work for ICs.
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By Amelia Dalton
What do electrostatic transduction, non-linear MEMS sensors, caffeine dosing strategies, and a glowing Death Star have in common? This here podcast! First up, we explore the Global MEMS Design Contest with Christine Dufour (Coventor – A LAM Research Company). Christine and I discuss the details of the winning designs and how design contests foster innovation in the electronic engineering ecosystem. Also this week, we check out an algorithm developed by the United States Army that aims to “optimize an ideal caffeine dosage strategy” and take a closer look at the “The World’s Most Accurate Death Star Replica Firepit”.
Listen to this episode of fish fry here
GLOBAL MEMS DESIGN CONTEST WINNERS ANNOUNCED
May 9, 2018 8:13am by Mathew Dirjish | Sensors Magazine Online
Global MEMS Design Contest winners announced
May 9, 2018 by Fabio Boiocchi | Elettronica News
MEMS bent on many design kits
May 9, 2018 by Veijo Ojanpera
New ideas for MEMS
May 9, 2018 by Irish Stroh | Markt & Technik
Cadence: Winner of Global MEMS Design Contest
May 9, 2018 by Hartmut Rogge | Channel-e
Winner of the global MEMS design contest
May 9, 2018 | Electronic Specifier Germany
Motion harvester wins MEMS design contest
May 9, 2018 by Chris Edwards | Tech Design Forum
Winner of MEMS competition
May 10, 2018 by Göte Fagerfjäll | Elektronik i Norden
Global MEMS design contest winners announced
May 11, 2018 | Engineer News Network
Global MEMS contest design winners announced
May 14, 2018 by Amy Wallington | Components in Electronics
Cadence Announces the Winner of the MEMS Circuits-Based Design Contest
May 16, 2018 | Electronique Composants & Instrumentation
Cadence Design Systems, Coventor, X-FAB and Reutlingen University have announced the grand prize winner of the Global MEMS Design Contest 2018 at CDNLive EMEA 2018, the Cadence annual user conference.
A team from ESIEE Paris and Sorbonne University received the grand prize award for designing a MEMS-based energy harvesting product using electrostatic transduction.
read the full article here.