Electronic Engineering Journal | By Bryon Moyer | November 28, 2016
If it’s November, that means it’s time for the C-level folks in the MEMS and sensor industries to assemble and assess the state of the industry at the MEMS Executive Congress. Because of the higher average title of these attendees, it has a very different feel from other conferences. And it mostly happens in lockstep (without five different tracks and an exhibit floor as distractions). Which makes it a bit easier to get a read on things. Click to Read More…

EE Times | By R. Colin Johnson | November 22, 2016
LAKE WALES, Fla. — Coventor’s SEMulator3D began as a tool for designing microelectromechanical systems (MEMS), then evolved to semiconductor equipment companies, chip makers and foundries for the 3-D structures in FinFETS, 3-D NAND and HD disk-heads. Now every major company in the MEMS and semiconductor supply chain uses Coventor’s tools (with over half of their customers making semiconductors instead of MEMS). Next Coventor is anticipating the mixed analog/digital/photonic chips of the future by adding modeling of the optical channels, mixers, and other specialized functions for the coming photonic era. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | November 21, 2016
After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology. Metrology, the science of measurements, is used to characterize tiny films and structures. Click to Read More…

MEMS & Sensors Industry Group | November 11, 2016
MEMS & Sensors Industry Group (MSIG)’s MEMS & Sensors Executive Congress™ — held November 9-11 in Scottsdale, AZ — gave innovative developers of driverless vehicles and drone-defense makers — as well as one of the world’s top carriers — a ready audience of industry execs as they shared their wants for new MicroElectroMechanical Systems (MEMS)/sensors for future products. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | November 7, 2016
For years, extreme ultraviolet (EUV) lithography has been a promising technology that was supposed to help enable advanced chip scaling. But after years of R&D, EUV is still not in production despite major backing from the industry, vast resources and billions of dollars in funding. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | October 20, 2016
Amid a tumultuous business environment, the silicon foundry industry is projected to see steady growth in a number of process segments in 2017.  As in past years, the foundry market is expected to grow faster than the overall IC industry in 2017. But at the same time, the IC industry—the foundry customer base—continues to witness a frenetic wave of merger and acquisition activity. Basically, the consolidation translates into a dwindling customer base for foundry vendors. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | October 20, 2016
Nearly 10 years ago, the industry rolled out a potentially disruptive technique called inverse lithography technology (ILT). But ILT was ahead of its time, causing the industry to push out the technology and relegate it to niche-oriented applications. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | September 22, 2016
Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts. For one thing, the features on the photomask are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fabrication facility. And finally, mask tool costs are soaring at each node. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | September, 22 2016
In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing. There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy. Click to Read More…

Semiconductor Engineering | By Ed Sperling | August 23, 2016
Coventor’s CEO talks about how to get chips through manufacturing more quickly. Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation. Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | August 18, 2016
Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner. The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node. Click to Read More…

Silicon Semiconductor | July 28, 2016
Coventor, Inc., supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), has announced its SEMulator3D 6.0 won the 2016 “Best of the West” award sponsored by Solid State Technology and SEMI at SEMICON West. This industry award recognizes the product and technology developments that contributed the most significant improvements to the electronics manufacturing supply chain. Coventor’s SEMulator3D was selected for the significant financial, scientific and social impact it has had on the industry. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | July 21, 2016
A surge in demand for consumer electronics, communications ICs, sensors and other products has created a shortage in 200mm fab capacity that shows no signs of abating. None of these chips need to be manufactured using the most advanced processes, and there have been enough tweaks to processes at established nodes to eke even more out of existing processes. But that has left chipmakers struggling to procure 200mm equipment for those fabs as demand for chips at these older nodes continues to rise. Click to Read More…

Electronic Engineering Journal | By Bryon Moyer | July 18, 2016
Astronomy bestows lavish breathless anticipation upon one of the great events of the universe: two galaxies running into (or through) each other. The thing is, it happens breathtakingly slowly – each stately galaxy spinning away, the distance between them slowly evaporating. Watching it is something of a sampling exercise: see where they are; nap for a couple of centuries. Wake, see that, yup, they’re a little closer; nap. Wake again, grab a new beer, and doggonnit if they aren’t just a wee bit closer yet. Basketball it’s not. Click to Read More…

Solid State Technology | By Pete Singer, Editor-in-Chief | July 18, 2017
On Wednesday, Solid State Technology and SEMI announced the recipient of the 2016 “Best of West” Award — Coventor — for its SEMulator3D. The award recognizes important product and technology developments in the electronics manufacturing supply chain. The Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact. Click to Read More…

Electronic Products | By Jim Harrison | July 15, 2016
At SEMICON West, industry organization SEMI provided some industry insights with two presentations. SEMI has more than 2,000 member companies in the science and business of electronics manufacturing. The first talk was by Denny McGuirk, President and CEO, who noted the two main happenings in the semiconductor industry: massive industry consolidation and realignment ($100 billion in M&A) and increasing demand for IoT and smart manufacturing. Click to Read More…

Semiconductor Engineering Journal | By Ed Sperling | June 27, 2016
The atomic layer etch (ALE) market is starting to heat up as chipmakers push to 10nm and beyond. ALE is a promising next-generation etch technology that has been in R&D for the last several years, but until now there has been little or no need to use it. Unlike conventional etch tools, which remove materials on a continuous basis, ALE promises to selectively and precisely remove targeted materials at the atomic scale. Click to Read More…

Electronic Engineering Journal | By Amelia Dalton | June 27, 2016
Sometimes the road less traveled is less traveled for a reason. (Jerry Seinfeld) We know what roads will lead us to the 7nm semiconductor node and frankly, they’re not all that scenic. In this week’s Fry Fry, we tackle the trials and tribulations of this tiny titan with David Freid from Coventor 7nm?” Click to Listen…

Electronic Component News | By Product Design and Development Staff | June 20, 2017
In the Product Design & Development Brainstorm, we talk with industry leaders to get their perspective on issues critical to the design engineering marketplace. In this issue, we ask: What are some of the key technology trends that will shape the evolution of the wearables market? Click to Read More…

Tech Design Forum | By Luke Collins | June 10, 2016
Coventor has updated its SEMulator3D virtual fabrication tool so it can extract predicted resistance and capacitance values from its models. The analysis tool could be used to speed up the availability of early PDKs for rapidly evolving processes. SEMulator3D abstracts IC manufacturing steps into behavioral models, so that it can simulate a whole process in a ‘virtual fab’. Click to Read More…

EE Times | By R. Colin Johnson | June 7, 2016
LAKE WALES, Fla.—What began as a microelectromechanical systems (MEMS) 3-D design tool has transformed into a 3-D semiconductor design tool which has accordingly added Electrical Analytics to the latest version six of Coventor’s SEMulator3D. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | May 25, 2016
The advent of the Internet of Things will open up a slew of new opportunities for MEMS-based sensors, but chipmakers are proceeding cautiously. There are a number of reasons for that restraint. Microelectromechanical systems are difficult to design, manufacture and test, which initially fueled optimism in the MEMS ecosystem that this market would command the same kinds of premiums that analog designs have been able to maintain. Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | May 23, 2016
In chip scaling, there is no shortage of challenges. Scaling the finFET transistor and the interconnects are the biggest challenges for current and future devices. But now, there is another part of the device that’s becoming an issue—the contact. Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | May 23, 2016
In 2013, Samsung reached a major milestone in the IC industry by shipping the world’s first 3D NAND device. Now, after some delays and uncertainty, Intel, Micron, SK Hynix and the SanDisk/Toshiba duo are finally ramping up or sampling 3D NAND. Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | May 19, 2016 By Mark Lapedus
Directed self-assembly (DSA) was until recently a rising star in the next-generation lithography (NGL) landscape, but the technology has recently lost some of its luster, if not its momentum. So what happened? Nearly five years ago, an obscure patterning technology called DSA burst onto the scene and began to generate momentum in the industry. Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | May 19, 2016 By Mark Lapedus
The leading edge of the chip market increasingly is divided over whether to move to finFETs or whether to stay at 28nm using different materials and potentially even advanced packaging. Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | May 10, 2016
Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation. SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm? Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | April 27, 2016
Extreme ultraviolet (EUV) lithography is still not ready for high-volume manufacturing, but the technology is at least moving in the right direction. Both the EUV light source and resists are making noticeable progress, even though there are still challenges in the arena. And then, there is the EUV mask infrastructure, which also has some gaps. Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | April 21, 2016
Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next.
At 10nm and beyond, IC vendors are determined to scale the two main parts of the finFET structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects may continue to fall further behind the curve. Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | April 21, 2016
Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era. The first finFETs were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled. Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | March 17, 2016
The multi-beam e-beam mask writer business is heating up, as Intel and NuFlare have separately entered the emerging market. In one surprising move, Intel is in the process of acquiring IMS Nanofabrication, a multi-beam e-beam equipment vendor. And separately, e-beam giant NuFlare recently disclosed its new multi-beam mask writer technology. Click to Read More…

EE Times | By R. Colin Johnson | March 16, 2016
LAKE WALES Fla.—Simplifying and popularizing microelectromechanical system (MEMS) design is the goal of the MEMS Design Contest announced yesterday (March 16) at the conference titled Data Automation and Test in Europe (DATE 2016, March 15 to 17, Dresden, Germany). More specifically, the contest encourages chip designers to add MEMS blocks to a chip design, using tools designed for the purpose. Sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, the contest will feature a special process design kit (PDK) that the winners will use to fabricate their MEMS chip at X-Fab. If interested attend the DATE session Launch of the Worldwide MEMS Design Contest. Click to Read More…

Semiconductor Engineering Journal | By Mark Lapedus | March 7, 2016
Chipmakers are ramping up their 16nm/14nm logic processes, with 10nm expected to move into early production later this year. Barring a major breakthrough in lithography, chipmakers are using today’s 193nm immersion and multiple patterning for both 16/14nm and 10nm. Now, chipmakers are focusing on the lithography options for 7nm. Click to Read More…

Desktop Engineering | By Tom Kevan | March 1, 2016
It all started with smartphones and airbags. Design engineers began to integrate sensors in growing numbers into such systems to enable smarter performance. These applications mark the prelude to what Alberto Sangiovanni-Vincentelli, a professor at University of California, Berkeley, describes as a “sensory swarm” — a flood of heterogeneous sensors interfacing the cyber and physical worlds. By 2025, experts predict that the swarm could number as many as 7 trillion devices. Click to Read More…

Semiconductor Engineering & Design Community | February 25, 2016
Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016. The objective of this contest is to encourage greater ingenuity with regard to the integration of MEMS devices and mixed-signal CMOS blocks. To kick off the contest, an informative session will be held in the Exhibition Theatre on Thursday, March 17, 2016 from 14:00 to 17:30 and is open to all DATE attendees free of charge. Click to Read More…

Semiconductor Engineering & Design Community | By Jeff Dorsch | February 25, 2016
The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race. It’s becoming clearer, however, that 193i immersion and extreme-ultraviolet lithography will co-exist in the future, while directed self-assembly, nanoimprint lithography, and maybe even electron-beam direct-write technology will fit into the picture, too. Click to Read More…

Tech Design Forum | By Luke Collins | February 23, 2016
Directed self-assembly (DSA) techniques may offer similar advantages in terms of process variation control as EUV lithography, according to a study carried out using 3D behavioral process modeling techniques. This could reduce fab cycle times, ease process integration and save costs in advanced semiconductor processes, especially for DRAMs, whose regular structures are well-suited to the use of DSA. Click to Read More…

SemiWiki.com | By Scotten Jones | January 20, 2016
On Tuesday evening December 8th at IEDM, Coventor held a panel discussion entitled the “The Last Half Nanometer”. Coventor is a leading provider of simulation software used to design processes. This is my third year attending the Coventor panel discussion at IEDM and they are always excellent with very strong panels and discussion. The panel was made up of David Fried CTO of Coventor, Alek Chen from ASML, Aaron Theon of IMEC, and Subramanian Iyer from UCLA. Subramanian acted as both a panelist and the moderator. Click to Read More…