Semiconductor Engineering | By Ed Sperling | October 21, 2019
The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes.  Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or in materials or unusual use cases. In the past, most of these have not impacted yield, but the equation is beginning to change for a number of reasons. Click to Read More…

Electronic Engineering Journal | By Bryon Moyer | August 26, 2019
One of the tricky bits when launching a new process is figuring out what the process window is. For anyone new to the concept, the window is the range of variation that’s allowable for a given process parameter. Go outside that range, and a die – or a wafer – or a lot – may fail. Click to Read More…

Semiconductor Engineering | By Ed Sperling | July 24, 2019
Reducing process margin could provide an entire node’s worth of scaling benefits. Enough margin exists in manufacturing processes to carve out the equivalent of a full node of scaling, but shrinking that margin will require a collective push across the entire semiconductor manufacturing supply chain. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | July 12, 2019
The Semicon West trade show took place this week in San Francisco. There were a slew of announcements at the event. Applied Materials, Coventor, Intel, KLA and others made various announcements. Click to Read More…

ChipEstimate.com| By Nanette Collins| July 1, 2019
MILPITAS, CALIF. – July 1, 2019 – The exhibit floor at ES Design West will be a showplace of companies that span the entire electronic system design ecosystem including IP, EDA, embedded software, design services, design infrastructure and the cloud presenting system-centric commercial solutions for complex chip design. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | June 24, 2019
David Fried, vice president of computational products at Lam Research, looks at shrinking tolerances at advanced processes, how that affects variation in semiconductor manufacturing, and what can be done to achieve the benefits of scaling without moving to new transistor architectures. Click to Watch Video…

Semiconductor Engineering | By Mark Lapedus | May 23, 2019
Amid the ongoing memory downturn, 3D NAND suppliers continue to race each other to the next technology generations with several challenges and a possible shakeout ahead. Click to Read More…

Semiconductor Engineering | By Ed Sperling | April 24, 2019
Equipment and tools vendors are starting to focus on data as a means of improving yield, adding more sensors and analysis capabilities into the manufacturing flow to circumvent problems in real time. How much this will impact the cost of developing complex chips at leading-edge nodes, and in 2.5D and 3D-IC packages, remains to be seen. Click to Read More…

Semiconductor Engineering | By Christine Dufour and Viraja Sharma | April 18, 2019
New MEMS-based products are constantly emerging, fueled by the Internet of Things (IoT), autonomous driving, smart manufacturing and healthcare applications. The MEMS pressure sensor market is no exception to this trend. Its growth has been driven mainly by automotive applications such as tire pressure management system (TPMS) regulations in China, fuel and ignition systems, thermal systems, oil-pressure monitoring, and indoor and outdoor navigation systems. Click to Read More…

Semiconductor Engineering | By Ed Sperling and Mark LaPedus | March 20, 2019
Packaging is emerging as one of the most critical elements in semiconductor design, but it’s also proving difficult to master both technically and economically. The original role of packaging was simply to protect the chips inside, and there are still packages that do just that. But at advanced nodes, and with the integration of heterogeneous components built using different manufacturing processes, packaging is taking on a much broader and more strategic role. Many of the new packages are application-specific, and they are an integral part of the system architecture. They can help channel heat, improve performance, help to reduce power, and even safeguard signal integrity. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | March 12, 2019
Chipmakers are using more and different traditional tool types than ever to find killer defects in advanced chips, but they are also turning to complementary solutions like advanced forms of machine learning to help solve the problem. Click to Read More…

Semiconductor Engineering | By Ed Sperling | February 21, 2019
Semiconductor equipment vendors are starting to add more sensors into their tools in an effort to improve fab uptime and wafer yield, and to reduce cost of ownership and chip failures. Massive amounts of data gleaned from those tools is expected to provide far more detail than in the past about multiple types and sources of variation, including when and where that variation occurred and how, when and why equipment failures occur. Click to Read More…

Semiconductor Engineering | By Ed Sperling | January 24, 2019
Variation is becoming more problematic as chips become increasingly heterogeneous and as they are used in new applications and different locations, sparking concerns about how to solve these issues and the full impact will be. Click to Read More…

Semiconductor Engineering | By Mark Lapedus | January 2, 2019
The growing challenges of traditional chip scaling at advanced nodes are prompting the industry to take a harder look at different options for future devices. Scaling is still on the list, with the industry laying plans for 5nm and beyond. But less conventional approaches are becoming more viable and gaining traction, as well, including advanced packaging and in-memory computing. Some options are already here, while others are still in R&D and require more funding to get off the ground. Click to Read More…