Semiconductor Engineering | By Ed Sperling | December 21, 2020
Variation is becoming a much bigger and more complex problem for chipmakers as they push to the next process nodes or into increasingly dense advanced packages, raising concerns about the functionality and reliability of individual devices, and even entire systems. Click to Read More…

EP&T Magazine | November 18, 2020
Coventor, a Lam Research Company, and CMC Microsystems, manager of Canada’s National Design Network (CNDN), announced an expanded technology sharing collaboration, bringing advanced software platforms to Canadian academic and startup organizations. CMC Microsystems will now offer Coventor’s SEMulator3D process modeling software to CNDN participants, adding to the existing availability of the CoventorMP MEMS Design Platform. Click to Read More…

Semiconductor Digest | November 17, 2020
Coventor, a Lam Research Company, and CMC Microsystems, manager of Canada’s National Design Network (CNDN), today announced an expanded technology sharing collaboration, bringing advanced software platforms to Canadian academic and startup organizations. CMC Microsystems will now offer Coventor’s SEMulator3D® process modeling software to CNDN participants, adding to the existing availability of the CoventorMP® MEMS Design Platform. Click to Read More…

EE Times Japan | September 23, 2020
高度なCMOSプロセスの微細化やメモリ技術の進化に伴い、デバイス製造における構造がますます複雑化しています。例えば、NAND型フラッシュメモリの場合、垂直方向に拡張するためにメモリスタックの積層数を増やすことによって、面積の微細化を継続しながら、高アスペクト比のエッチングパターンとステアケースにおけるコンタクト層の増加を実現するという課題が生じています。また、微細化の課題を解決するために特別なインテグレーションとパターニングスキームの採用は、デザインルールにおける課題を生み出しています。 Click to Read More…

SEMICON West | July 21, 2020
Coventor, a Lam Research Company, the global market leader in design automation solutions for microelectromechanical systems (MEMS) and virtual fabrication of MEMS and semiconductor devices, today announced the immediate availability of CoventorMP 1.3 – the newest version of its MEMS design automation platform. Click to Read More…

Sensors Daily | By Mat Dirjish | July 20, 2020
Coventor debuts CoventorMP 1.3 as the latest version of its MEMS design automation platform. The application adds MEMS+ features, performance improvements, and capabilities, that address the need to quickly and easily design highly complex MEMS devices and improve the performance and reliability of next-generation MEMS devices in a wide range of applications. Click to Read More…

Embedded | By Nitin Dahad | July 20, 2020
For engineers designing and integrating for microelectromechanical systems (MEMS) devices such as motion sensors, microphones, timing devices and energy harvesters into other systems and circuits, Coventor, a Lam Research company, has released a new version of its MEMS design automation platform. Click to Read More…

Semiconductor Digest | By Shannon Davis | July 20, 2020
“The latest CoventorMP product release delivered a breakthrough in MEMS design capabilities…ADI has greatly benefitted from Coventor’s advances in MEMS design automation, and we look forward to continuing our long-term collaboration with Coventor.” Click to Read More…

EEWorld Online | By Aimee Kalnoskas | July 20, 2020
Coventor, a Lam Research Company, announced the immediate availability of CoventorMP 1.3 – the newest version of its MEMS design automation platform. With added MEMS+ features, performance improvements, and new capabilities, CoventorMP 1.3 addresses the need to quickly and easily design highly complex MEMS devices and improve the performance and reliability of next-generation MEMS devices in consumer, automotive, aerospace, industrial and IoT applications. Click to Read More…

EE Times Japan | June 24, 2020
我们不断向先进的CMOS的微缩和新存储技术的转型，导致半导体器件结构的日益复杂化。例如，在3D NAND内存中，容量的扩展通过垂直堆栈层数的增加来实现，在保持平面缩放比例恒定的情况下，这带来了更高深宽比图形刻蚀工艺上的挑战，同时将更多的阶梯连接出来也更加困难。人们通过独特的整合和图案设计方案来解决工艺微缩带来的挑战，但又引入了设计规则方面的难题。 Click to Read More…

Semiconductor Engineering | By Mark Lapedus | May 21, 2020
Used in advanced fabs, EUV involves a giant and expensive lithography scanner, which patterns tiny features on chips at 13.5nm wavelengths. EUV is one of several fab tools used in chip scaling. This is where you shrink different chip functions at each node and pack them onto a monolithic die. But chip scaling is becoming more expensive at each generation, and the benefits are diminishing. Click to Read More…

Semiconductor Engineering | By Ed Sperling | May 12, 2020
Consistency, completeness and sharing of data can provide insights about a chip’s design, health and interactions, but it’s not that simple. Click to Read More…

Semiconductor Engineering | By Ed Sperling | April 16, 2020
One of the fundamental components of a semiconductor, the interconnect, is undergoing radical changes as chips scale below 7nm. Click to Read More…

Semiconductor Engineering | By Mark Lapedus and Ed Sperling| April 16, 2020
Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Click to Read More…