China Semiconductor Technology International Conference (CSTIC) in SEMICON China 2021

Coventor and Lam will have 5 SEMulator3D presentations at the 2021 China Semiconductor Technology International Conference (CSTIC) conference:

• “Advancing to the Next Node and Competing Globally Using Virtual Fabrication” – Authors: Joseph Ervin
• “The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance” – Authors: Qingpeng Wang, Yu De Chen, Cheng Li, Rui Bao, Jacky Huang and Joseph Ervin
• “Exploring Gate-Cut Patterning Approaches Using Simulation and Defect Modelling” – Authors: Li Fei Sun, Qing Peng Wang, Ji Hong Zhang, Yu Shan Chi
•  “Simulation-Assisted Ion Angle Tuning in High Aspect-ratio (HAR) Etch for Wafer Edge Bottom Etch Enhancement” – Authors: Jingdong Yan, Run Zhang, Zhijie Hao
• “FinFET Gate Etch Modeling by Coventor SEMulator3D®” – Authors: Hexin Zhou, Qingpeng Wang, Dongyang Yu, Andrew Li