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In 5 nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24 nm. Fin depopulation is mandatory to enable area scaling, but it becomes challenging at small pitches. In the first part of our study, we simulate a FinFET process flow with various fin cut approaches to obtain a 3D model of a FinFET SRAM device. Layout dependent effects on silicon and process non-idealities are characterized in a second part and used to calibrate the 3D model. In the third part of our work, a process sensitivity analysis is performed to compare the impact of overlay and CD variations on various fin cut options.
© (2019) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
S. Baudot, A. Soussou, A. P. Milenin, T. Hopf, S. Wang, P. Weckx, B. Vincent, J. Ervin, and S. Demuynck, "Self-aligned fin cut last patterning scheme for fin arrays of 24nm pitch and beyond", Proc. SPIE 10960, Advances in Patterning Materials and Processes XXXVI, 109600N (25 March 2019); doi: 10.1117/12.2514927;
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