By Ed Sperling
By Ed Sperling
David Fried, CTO at Coventor, a Lam Research Company, sat down with Semiconductor Engineering to talk about how AI and Big Data techniques will be used to improve yield and quality in chip manufacturing. What follows are excerpts of that conversation.
SE: We used to think about manufacturing data in terms of outliers, but as tolerances become tighter at each new node that data may need to be examined even within what is considered the normal range. What’s the impact of that on manufacturing?
Fried: When I started in CMOS at 200mm, there was some data on the tools in the fab, but by and large, we were losing it as soon as it was created. When we went to 300mm, we got better at putting sensors on tools, generating data, and in some cases looking at it.
By Paula Doe
The fast-maturing infrastructure now enabling analysis of exponentially larger data volumes brings the microelectronics industry to an inflection point, where the winning companies will be the first to master the use of this data to solve the industry’s emerging challenges. SEMI expands its coverage of these vital issues with a Smart Manufacturing Pavilion and three days of talks SEMICON West, July 10-12 in San Francisco.
While deep learning is starting to be applied to image recognition for wafer inspection, it is also being considered for sequential pattern recognition in order to evaluate equipment parameter traces. The next emerging applications will start to use those learned patterns to predict outcomes, and then use those predictions to automate process control. One early application of deep learning is IC process development.
By Bryon Moyer
Two years ago at the annual DATE conference in Europe, a MEMS design contest was announced. Sponsored by Reutlingen University, Coventor, X-Fab, and Cadence, the goal was to stimulate creative ideas for MEMS technology. The sponsors each had a part: Coventor and Cadence provided tools for the design process, and X-Fab signed up to build the winning design. Reutlingen University helped with the organizing efforts.
Well, the winners were recently announced, and we’re going to look through the projects of the top three contestants. The problems they tackle vary widely, and they’re not necessarily what you might be expecting. The projects are interesting in their own right, which is why we’re having this little chat.
By MARK LAPEDUS
Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects.
That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resistance in chips. It’s still too early to say if the changes will work. Early reviews are mixed.
To be sure, though, there is an inflection point taking place in leading-edge chips, which consist of three parts—the transistor, contacts and interconnects. The transistor resides on the bottom of the structure and serves as a switch. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another.
By MARK LAPEDUS
As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm.
Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-popping $1 billion. In addition, there are also several uncertainties at 3nm that could change everything overnight.
That hasn’t sidelined anyone yet, however. Samsung and GlobalFoundries separately announced plans to develop a new transistor technology called a nanosheet FET, with so-called variable widths at 3nm. Samsung, for one, hopes to deliver a PDK (version .01) by 2019, with plans to move into production by 2021. Meanwhile, TSMC is exploring nanosheet FETs and a related technology, nanowire FETs, at 3nm, but it has not announced its final plans. Intel, meanwhile, isn’t talking about its plans.
SEMICON West Preview: Smart Microelectronics Manufacturing Builds the Infrastructure to Enable AI Applications
By Paula Doe
The fast-maturing hardware and software that are enabling practical applications of equipment intelligence and machine learning mean disruptive change for microelectronics manufacturing. But first comes the basic work of building the basic infrastructure, figuring out IP separation, and learning to solve physical problems in the digital world.
Just how much can the semiconductor industry leverage industrial IoT practices from other industries? Common wisdom may be that industrial software solutions aren’t well suited to the IC sector’s complex needs. But GE Digital enterprise account executive Luke Smaul, currently working with Intel, argues that semiconductor fabs and toolmakers are dealing with similar issues as GE did when it first started working with Delta Airlines to monitor the GE engines on Delta planes. Smaul will speak at SEMICON West about GE’s work with Intel over the past few years and, in particular, how its solution for cloud security and IP separation can work for ICs.
By Amelia Dalton
What do electrostatic transduction, non-linear MEMS sensors, caffeine dosing strategies, and a glowing Death Star have in common? This here podcast! First up, we explore the Global MEMS Design Contest with Christine Dufour (Coventor – A LAM Research Company). Christine and I discuss the details of the winning designs and how design contests foster innovation in the electronic engineering ecosystem. Also this week, we check out an algorithm developed by the United States Army that aims to “optimize an ideal caffeine dosage strategy” and take a closer look at the “The World’s Most Accurate Death Star Replica Firepit”.