Big Trouble At 3nm

By MARK LAPEDUS

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm.

Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-popping $1 billion. In addition, there are also several uncertainties at 3nm that could change everything overnight.

That hasn’t sidelined anyone yet, however. Samsung and GlobalFoundries separately announced plans to develop a new transistor technology called a nanosheet FET, with so-called variable widths at 3nm. Samsung, for one, hopes to deliver a PDK (version .01) by 2019, with plans to move into production by 2021. Meanwhile, TSMC is exploring nanosheet FETs and a related technology, nanowire FETs, at 3nm, but it has not announced its final plans. Intel, meanwhile, isn’t talking about its plans.

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