EDA Tool Aims at 10-Nanometer 3-D

By Colin Johnson
Electronic Engineering Times

Reaching the advanced semiconductor process nodes at 22-nanometer and beyond requires accurate three-dimensional (3-D) models of the proposed physical structures to obviate the need for repeated trial-and-error design cycles. In fact, the International Technology Roadmap for Semiconductors has designated modeling 3D physical structures as a “grand challenge” at advanced processing nodes.

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