By Ed Sperling
Coventor’s CEO talks about how to get chips through manufacturing more quickly.
Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation.
SE: Why does it take so long to get a chip all the way through to manufacturing?
Jamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new things and possibilities. There is the manufacturing side, which is going to take the normal amount of time for getting things ramped up. And then there is the ‘in-between’ phase—the technology development. It may take four years before a product reaches the market. That ‘in-between’ phase is where a lot of the hard work gets done, using a lot of short loop and learning cycles. You’re not just trying to create one device. You’re trying to create a billion devices. You are trying to use that process to address different types of structures, not just for one finFET or memory, but all the complexities and devices that might go into that process, as well. Then you have the BEOL and such. There is a lot of work that is going on during those four years. Traditionally, the way things worked was that it was these short loop cycles of one to three months. Then there were test chips, which might be out once per year. But it would take about three or four of those one-year cycles to be able to get them through, along with lots of the little cycles of learning. Our customers believe they can change this ‘in-between’ period to reduce the amount of time. We had a customer that did these virtual fabrications and cut nine months out of their development cycle.