Panel Probes Chipmaking Challenges

EE Times
by George Leopold on December 16, 2013

WASHINGTON, D.C. — The job of making advanced chips and finding ways to collaborate on the work is getting tougher, according to a panel of veteran semiconductor researchers who gathered just outside the International Electron Devices Meeting in Washington last week.

Moderator David Fried, chief technologist of Coventor, a supplier of 3D modeling and simulation software, asked panelists to describe the biggest technical challenges they face as well as the key challenges to keeping their projects on schedule. The latter question is critical, given the growing industry perception that the pace of chip scaling is slowing. That is making it harder for IC makers to push designs based on ever-shrinking geometries out the door.

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