Q&A: MEMS Begin to Enter the Semiconductor Design Mainstream

By Richard Goering on December 11, 2013

Micro-electrical mechanical systems (MEMS) have been a niche technology for many years, but a new generation of MEMS ICs is emerging, according to Mike Jamiolkowski, CEO of Cadence partner and MEMS tool provider Coventor. Barriers to the use of MEMS technology, such as the need for PhD-level experts and non-reusable foundry processes, are starting to ease.

In this interview Jamiolkowski talks about new trends in the MEMS market, discusses his company’s MEMS+ tools and how they work with the Cadence Virtuoso platform, and notes a new MEMS+ capability to output reduced order models in the Verilog-A language.

Q: Mike, when did Coventor get started and what does it offer today?

A: Coventor was started 17 years ago. I was previously a founder of ISS [Integrated Silicon Systems], which was an EDA company. I identified some technology at MIT that provided design tools for MEMS. I licensed the technology and received a fair amount of funding to evolve it, and we became a leading provider of MEMS tools.

The tool suite we have now is much more advanced than what came out of MIT. We have the MEMS+ toolset, which is a descendant of our Architect environment. We realized that customers who wanted to integrate MEMS and ICs really couldn’t use Architect, so we adapted the platform to interface with Virtuoso and also with MATLAB and Simulink.

A second, complementary product offering is CoventorWare, which does detailed simulations of coupled electro-mechanical physics. A third offering is on the process side. Our product SEMulator3D is used by MEMS companies to design devices as well as the process, because the device and process are very closely linked in MEMS. We also evolved that capability to support customers who are developing advanced semiconductor technologies, such as FinFETs.

Q: A few years ago it seemed that MEMS were relegated to a handful of high-volume applications. Where are they showing up now?

A: The categories of MEMS devices have evolved dramatically. The use of gyroscopes, accelerometers, magnetometers, and microphones has dramatically increased the number of MEMS devices in volume, as well as revenue, over the past few years.

Apple and Samsung are using MEMS in smartphones and tablets. In 2012 Apple purchased over $700M worth of MEMS for mobile consumer devices, and Samsung jumped to $500M. Apple’s M7 chip is a processor to manage sensor input. Companies now want to integrate MEMS more deeply and to make products cheaper. And we are starting to see much stronger interest from foundries.

One of the big opportunities we’ve identified is the growing importance of the Chinese market. They have a lot of second- and third-tier mobile device manufacturers and they’re demanding a lot more volume. I think China will be a very high growth area for MEMS in mobile devices.

Q: Do MEMS still require specialized process development?

A: Processes are still MEMS-specific, but some are now reusable. Foundries, of course, are interested in CMOS processes, and they want to get away from processes that are MEMS-specific. With more customers and more integration, changes are occurring and platforms are starting to be built.

Q: What about the requirement for PhD-level experts for MEMS design?

A: MEMS still requires expertise, but not as much as three years ago. We have promoted the concept of “democratization” of MEMS using tools and libraries. As a result, reuse is benefiting companies so they don’t have to have PhD-level expertise across the board.

Q: Let’s talk about design tools for a moment. The traditional MEMS design approach uses finite element analysis, which is slow. The alternative has been the use of simplified, handcrafted models. What does MEMS+ offer that’s different?

A: We use high-order, nonlinear finite elements, so our models are more accurate than reduced order models and they simulate almost as fast. This gives designers the ability to explore design spaces and optimize designs much more rapidly. And our models can run efficiently in simulation tools like Simulink and Cadence Spectre. They are not quite as accurate as conventional finite element analysis models, but you can learn a lot more.

Or course we also support conventional finite element analysis with CoventorWare, which does detailed coupled electro-mechanical physics. But with MEMS+ we offer another level of hierarchy so you can model a bigger area, like a full gyroscope.

Q: MEMS+ is a model creation and analysis environment. How does it work with Virtuoso?

A: We have created a very tight link. Virtuoso users can import fully parametric MEMS+ models through a MEMS+ menu item that we insert in the Cadence Library Manager. During import, we generate a schematic symbol and netlist. IC designers can then place the symbol in their schematic and run whatever simulations are appropriate for their design. The parameters of the MEMS+ model can be adjusted via the usual dialog that’s available for any symbol in a Virtuoso schematic.

Q: You recently announced MEMS+ 4.0, which offers a new capability to export reduced order models in Verilog-A format. How will this be used?

A: Our MEMS+ models are fully nonlinear and they allow many thousands of degrees of freedom. They are very complex and accurate, but they can slow simulations. We’ve added capabilities to provide IC designers with a simplified model in Verilog-A format. These exported Verilog-A models can be used in Spectre or any other simulator that supports Verilog-A. It speeds up the simulations dramatically – there could be a 100X speed improvement.

MEMS engineers can still use MEMS+ models with all the degrees of freedom and nonlinearities to understand their device designs and perfect them. With the exported Verilog-A models, IC designers can do most of their simulations with the simplified models and only use the full MEMS+ models for extreme corner cases.

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