Listen to a presentation on smart manufacturing and process modeling, and discover how they will revolutionize the development of semiconductor devices. Learn about the latest techniques in semiconductor process modeling, and how this new “virtual fabrication” technology can accelerate time to market for advanced semiconductor technologies. See real-life examples of virtual fabrication in action, during daily product demonstrations by Coventor at Booth #7847.
Mark your calendar to take advantage of these great opportunities to see and hear more about the future of semiconductor process development at SEMICON West 2017:
- Talk: “3D Model-Based Process Control for the Future of Smart Manufacturing” (Wednesday, July 12 from 2:00-2:30 p.m., SMART Journey Theater, Booth 7237 Moscone West, Level 1)
- Presentation: “Virtual Fabrication – Changing the Trajectory of Chip Manufacturing”(Wednesday, July 12 from 8:00 a.m. – 12:00 noon, New York State Nanotech Summit, PARC55 Hotel)
- Coventor Product Demonstrations (Booth #7847, Expo Floor)
Talk: “3D Model-Based Process Control for the Future of Smart Manufacturing”
Talk at SMART Journey: “3D Model-Based Process Control for the Future of Smart Manufacturing” at SEMICON West 2017
Wednesday, July 12 from 2:00-2:30 p.m. (Add to calendar)
SMART Journey: Meet The Experts – Smart Manufacturing
(SMART Journey Theater, Booth 7237, Moscone West, Level 1)
Dr. David M. Fried, is Chief Technology Officer (CTO) of Coventor, where he is responsible for the company’s strategic direction and implementation of its SEMulator3D virtual fabrication 3D process modeling solution. He leads the execution of technology strategy for technology platforms, partnerships, and external relationships. His expertise touches upon such areas as Silicon-on-Insulator (SOI), FinFETs, memory scaling, strained silicon, and process variability. Fried is a well-respected technologist in the semiconductor industry, with 56 patents to his credit and a notable 14-year career with IBM, where he was involved in successive process generations from 65-nanometer and lower. His most recent position was 22nm Chief Technologist for IBM’s Systems and Technology Group. He has Masters and Doctoral degrees in Electrical Engineering from Cornell University.
Advanced CMOS and memory technologies are becoming more structurally complex at an amazing rate. In Logic CMOS, just since 65nm, we have introduced embedded stressor source/drains, replacement high-k/metal-gates, FinFETs, complex multi-patterning schemes and many more structural innovations. NAND Flash has moved from conventional planar bit-lines to amazing 3D vertical bit-lines. DRAM continues (against all odds) to scale the bit-cell area, by burying the word-line, using amazingly high-aspect ratio capacitors and employing even more complex multi-patterning schemes. In all of these innovations, the semiconductor industry has taken effectively “top-down processing capabilities” from the planar era, and applied them to 3D structures, using surfaces (ie, sidewalls) that were not previously employed in devices. The next set of logic and memory innovations will certainly continue this trend, even employing the processes to use surfaces not-visible from top-down observation. Gate-All-Around (GAA) or Nanowire devices, for example, will have critical structural requirements underneath the device, representing a whole new paradigm of challenges both for metrology and process. Process enhancements, such as Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE) will be required. Metrology improvements from Optical Critical Dimension (OCD) and X-Ray measurement techniques (XRD, XRR,etc.) will be required. But the integrated complexity of these processes and patterning schemes will also drive a new era in advanced model-based process control that links the most advanced metrology and inspection results with the most advanced processes and equipment-level controls through feed-forward and feed-back control schemes.
Improved process yield in these advanced technologies will rely on the reduction of total process variation: tool-to-tool, lot-to-lot, wafer-to-wafer and across-wafer. Traditional process yield-ramp activity has been aimed at reducing the variation of all individual steps of the process. However, each of these individual processes and their associated control parameters have developed quite differently, resulting in unique opportunities to use some processes to compensate for uncorrectable variations arising from other processes. This improvement will not rely on static process adjustments, but on active control of many processes in real time. In order to deliver the control information for state-of-the-art processes on advanced device structures at the pace of manufacturing, high speed 3D process modeling is required. This 3D model will aggregate all of the measured variation from prior processing into a silicon-accurate prediction of the current state of the critical device structures on each wafer. Using computational methods to form this prediction on multiple critical design features at multiple locations on every wafer will enable a new level of feed-forward process control using the newest controls being deployed on process equipment today. This type of 3D model-based process control will be especially critical to the processes and structures where metrology is able to provide only partial information on the nature of variations, which is often the case in these advanced device structures of the next generation. Attendees at this discussion will gain an understanding of high-speed 3D process modeling and how model-based process control can be used to improve process yield of advanced semiconductor technologies.
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Presentation: “Virtual Fabrication – Changing the Trajectory of Chip Manufacturing”
Presentation: “Virtual Fabrication – Changing the Trajectory of Chip Manufacturing” in conjunction with SEMICON West 2017
Wednesday, July 12 from 8:00 a.m. – 12:00 noon (Add to calendar)
New York State Nanotech Summit
(PARC 55 Hotel, 55 Cyril Magnin Street, San Francisco, CA)
Pre-registration is required at no cost: https://sunypoly.edu/new-york-nanotech-summit/
Sandy Wen is a semiconductor and process integration engineer at Coventor. Previously, she worked at Applied Materials in the etch business group in various engineering functions, including chamber engineering and yield enhancement solutions. Sandy received her MS in EE from UCLA, and BS in EECS from UC Berkeley.
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Product Demonstrations during SEMICON West 2017
Coventor will be showcasing its novel techniques and methodologies to enable rapid acceleration from semiconductor concepts to manufacturing-ready products at SEMICON West 2017. Stop by our booth (#7847) to meet our technology experts, and sit in on a real-life product demonstration using the latest version of SEMulator3D.
The SEMulator3D platform provides a complete virtual fabrication environment
that parallels the capabilities of actual fabs. Use SEMulator3D to develop and
optimize manufacturing process flows, reducing time consuming and costly
experimental fabrication cycles.