Cadence® Integration

With MEMS+® for Cadence, designs created in MEMS+ Innovator can be automatically converted into IC compatible models and parametric layout (PCells) for the Cadence Virtuoso® design environment. MEMS+ for Cadence supports MEMS+IC co-simulation in Spectre and SpectreRF.

Software Evaluation

MEMS+IC Co-Simulation at Circuit Level

Most MEMS are comprised of a MEMS sensing or actuation element (the “MEMS device”), which is distinct from the accompanying electronics (the “IC”) that process the output signal from the device and/or control the device. MEMS product development within any organization divides the development similarly: the MEMS engineers who design the MEMS device, and IC engineers who design the surrounding sensing or control electronics.

IC engineers commonly use Cadence Virtuoso to design the analog/mixed-signal electronics that accompany a MEMS device. In order to succeed, IC engineers require fast and accurate models of the MEMS device in the Cadence model library. The MEMS model is then used as a component in the IC schematic to perform MEMS+IC cosimulation. The co-simulation is essential to verify the IC design and to predict yield sensitivity to manufacturing variations.

Key Features

  • Easy-to-use MEMS+ GUI in the Cadence Virtuoso Library Manager for automatic model and Pcell generation
  • User-defined number of symbol pins and parameters
  • Fast MEMS+IC circuit simulations
  • Accurate multi-physics modeling in Cadence simulators

The Coventor MEMS+ tool suite’s integration with Cadence facilitates the required model exchange from the MEMS engineer to the IC designer in a far more seamless manner than previously available in the marketplace. The generation of a Cadence library cell with both a parametric simulation model and layout Pcell is almost instantaneous and doesn’t require any FEM analysis or time-consuming reduced-order modeling.

Using the MEMS+ import GUI in the Cadence Library manager, a “symbol view”, a “model view” and a “layout view” can be created automatically from any given Innovator schematic.

MEMS+ Cadence Design Flow

The MEMS+ for Cadence design flow includes the following steps

Create a MEMS design in MEMS+ Innovator by selecting MEMS building blocks from the parameterized 3-D MEMS component library and assembling them into a MEMS device. As part of this process, the MEMS designer can specify which parameters will be exposed in the IC design environment.
When the design is complete, import the Innovator schematic into the Cadence Library manager. This will automatically create a Cadence netlist and symbol. The number and names of the symbol pins are controlled by the MEMS engineer, and represent electrical connections to the MEMS device.
Place the MEMS+ symbol in a schematic in the Virtuoso Schematic Editor. For the MEMS designer, there may be only a few components in the schematic necessary to provide electrical excitation, or electrical sensing of the output signal. For the IC designer, however, the schematic will include the complete IC design.
On completion of a simulation, view the simulation results for the MEMS device in the MEMS+ user interface. Within MEMS+, the user has the ability to animate the motion of the MEMS device.
At any time, create a parameterized layout cell (PCell) that can generate a layout of the MEMS device for use in Cadence Virtuoso..

MEMS+IC Simulation in Cadence Virtuoso

Key Features

  • Easily and quickly change your MEMS design
  • Very fast simulation runtimes, including transient simulations
  • Simulate your MEMS device with surrounding sub-system components
  • No finite element modeling required for MEMS+IC cosimulation

Key Benefits

  • Test many different design ideas quickly
  • Create a more complete simulation of device performance
  • Supports transient analysis of the MEMS device, difficult with FEM
  • Review coupled behavior of the MEMS device and sub-system
  • Generate results quickly and easily; FEM expertise not required

Once the 3-D model is created in MEMS+, it is ready for simulation. MEMS+ automatically creates the symbol for the schematic circuit design, including the assignment of electrical and mechanical pins. The models can be parameterized for materials, process and geometry, which means you never have to recreate the model to account for material, process or geometry changes or to vary any of these items.

The higher order finite elements in MEMS+ have been extensively tested and validated, and cover a broad variety of MEMS physics, such as electrostatics, mechanics, piezo-electric and contact modeling.

MEMS+ for Cadence lets you create MEMS device models that can be directly simulated with the IC that you are designing in the Cadence Spectre and SpectreRF simulators.


MEMS+ Innovator designs are assemblies of MEMS building blocks from our MEMS Model Library. Cadence models can be generated almost instantaneously by automatically assigning each used building block to the corresponding behavioral model. Simply by selecting an Innovator schematic, the MEMS+ import GUI in the Cadence Library Manager generates a schematic symbol and a model view. The material, process or geometrical variables set as “exposed” in the Innovator schematic are preserved in the created Cadence views.

Furthermore, the MEMS modeling environment gives the user full control over the number and names of the symbol pins created during the MEMS+ model import. MEMS+ for Cadence supports not only electrical pins, but also pins representing positions, angles, forces, torques, pressure loads, accelerations, angular rates, as well as capacitance and resistance outputs.

MEMS+ for Cadence is ideally suited for analog and digital circuit designs. The image features a MEMS+ created schematic symbol of an accelerometer, along with its surrounding sigma-delta control circuit comprised of components from the Cadence standard library.  The transient-response of the complete system can be simulated in under 10 seconds on a standard PC, due to the compact nature and efficiency of the MEMS+ models.


MEMS+IC Integration: Automated MEMS Layout PCells

Key Features

  • MEMS design polygons are visible within the Virtuoso layout environment
  • Boolean operations can be completed using solid modeling technology (without polygons), providing improved accuracy
  • The MEMS layout is available as a fully parameterized cell (Pcell) inside Virtuoso, simplifying and accelerating error checks and design modifications.

Key Benefits

  • Reduce layout drawing time
  • Simplify scripting requirements
  • Avoid errors in the MEMS design, along with connectivity of the MEMS layout to other circuit elements
  • Enable design reuse and improve design productivity

Tape-out is the final stage of the design cycle, the point at which the design layout is sent to the fab or foundry. It is also the most stressful time for the organization. Flexible parameterized cells reduce design entry time and design rule violations.

Parameterized cells (Pcells) provide an advanced level of design automation to minimize tedious and repetitive layout tasks. Pcells make it possible to change the size, shape or contents of each cell instance, without changing the original cell. They also raise the level of abstraction to the component level, which accelerates layout tasks and reduces design violations by simplifying complex shapes and devices that can then be generated, edited and managed with variable settings.

Coventor has developed a proprietary algorithm to generate parameterized layout cells from 3-D MEMS+ designs. These MEMS+ PCells can be instantiated with different values of the parameters. MEMS+ for Cadence drastically eases the pain of tedious manual Pcell creation. Thanks to the easy-to-use MEMS+ import GUI in the Cadence Library manger, Pcells can be created automatically from any given Innovator schematic.