Advanced Modeling Library

Plasma (dry) etches are critical for both FEOL and BEOL in semiconductor technology due to their flexibility, selectivity and directionality. By varying process parameters, etch engineers can achieve selectivity to specific materials of interest and control lateral etch bias, polymer formation and sputtering rate.

MultiEtch models multi-physics plasma etches on multi-material film stacks, using a relatively simple set of behavioral input parameters.  These input parameters include:

• Selectivity
• Lateral etch bias
• Taper angle
• Source directionality
• Source conformality, and
• Sputter rate

MultiEtch is capable of modeling very complex etches. Etch behavior can be specified on a per-material basis to model (for example) mask sputtering as well as taper due to polymer deposition. Limited visibility etching models can account for complex topographies and narrow mask openings, and can model profile position dependence of a material’s etch rate during the etch process.

Figure 1. M2-V1 process flow after (a) M2-L1 lithography, (b) M2-L2 litho, (c) V1 partial etch, (d) BLok open and (e) CuBS.

As an example, consider the M2-V1 process flow shown in Figure 1. This BEOL via chain integration features a trench-first metal hard mask with a self-aligned via (TFHM-SAV). Achieving a suitable chamfer on V1 is critical to avoid excessive electromigration and device failure. In this example, the chamfer is caused primarily by sputtering during the M2 over-etch (OE). The M2 OE is typically designed to avoid etching BloK, and as a result uses a strongly polymerizing chemistry that necessitates a higher bias voltage. Figure 2 shows the evolution of the M2 OE; note the formation of the chamfer and selectivity to the low-k ILD. Although the selectivity is very good, all materials on the wafer are etching.  Excessive over-etch can have negative ramifications on yield, such as break-through of the TiN hard mask.  These potential ramifications can be investigated and understood using MultiEtch.

Figure 2. Evolution of M2 OE. Note formation of chamfer on V1
and erosion of the TiN hard mask and BloK.

MultiEtch may also be used to model similarly interesting phenomena in STI, fin, gate, trench, contacts, and spacer etches throughout the entire process flow.

Selective epitaxial growth (epitaxy) was a key enabler for strained silicon technology in planar devices, and remains essential to achieving FinFET performance goals. Due to complex growth characteristics and limited ability to perform on-wafer metrology, epitaxy can be a significant source of both technology risk and device variation. Modeling can mitigate this risk through improved understanding of both growth characteristics and sources of variation.

SEMulator3D models epitaxy through characterization of the growth rates on the major silicon plane families. The structures achieved through epitaxy are typically strongly influenced by the slow-growing family of planes. Epitaxial behavior at interfaces with non-crystalline neighbor materials can also be important, and may be controlled in SEMulator3D through material-specific overgrowth parameters. Using this relatively small set of parameters, the physics-driven surface evolution modeling engine is able to model very dynamic, complex epitaxial growth characteristics.

Consider the example sub-22nm FinFET technology shown in Figure 3. This example technology uses spacer patterning for fin definition, embedded epitaxial source-drains (PFET only), differential replacement HKMG integration and self-aligned local interconnects.

Figure 3. 0.074 um2 SRAM cell in example process flow (a) Fin Definition and STI, (b) sacrificial gate module, (c) spacers and embedded SiGe, (d) Replacement Metal Gate and (e) Middle of Line modules

Figure 4 shows the evolution of epitaxy on a single fin. In this orientation, with fin sidewalls aligned with directions, the epitaxial growth is limited by slow-growing planes. The overgrowth characteristics on neighboring non-crystalline materials have a significant effect on the final dimensions of the epitaxial growth, as does the plane growth rate.

Figure 4. Evolution of epitaxial growth (a) under nominal process conditions, (b) with overgrowth on neighboring non-crystalline materials (popped), (c) with fastergrowth rate.

SEMulator3D includes modeling steps to predict the doping of materials and the dopant diffusion with subsequent thermal processing. The implanted dopant species and dose as well as the range, longitudinal and lateral straggles can be specified. This capability is not meant to replace the precision of long cycle-time TCAD implant modeling, but rather to enable fast turn-around analysis of dopant sensitivity and response to prior and subsequent processing. The Ion Implant and Thermal Diffusion process operations are implemented as new Process Editor steps, with their own behavioral parameters. Diffusion also requires the specification of Activation Energy (E_A) and Base Diffusivity (D₀) within the Materials Editor. SEMulator3D also integrates dopants in the Deposition and Selective Epitaxy process models. Gradient visualization capabilities in the SEMulator3D Viewer allows the user to visualize the dopant diffusion through the process integration and how process variations impact final dopant concentration. Dopant concentrations are displayed on any cross-section plane, while the rest of the 3D view displays the material model as always.

Various deposition techniques have been developed and used extensively in the modern semiconductor industry, and a deposited film profile can be determined by deposition physics in terms of surface reaction and mass transportation. It is a common observation that mass transportation limited deposition such as PVD and PECVD can have non-conformal step coverage, resulting in shadowing, bread-loaf effects or void formation in later processes.

Figure 1. Breadloaf effect and void formation in Mx Barrier/Cu Fill process

The Visibility Deposition process can incorporate directionality into the deposition to address this non-conformal process. Once deposition directionality is specified, the film thickness at each point on the wafer can be calculated through a function of the visibility to the deposition source of each point on the wafer surface. In addition, wafer position such as rotation, twist, and tilt are also supported in this model to simulate a practical deposition environment.

In CMOS source/drain engineering, recessing before selective epitaxial growth can contribute to channel strain and reduce short channel effects. One recessing method uses crystallographic or anisotropic etching with wet chemistries (such as TMAH or NH4OH) to expose {111} planes in crystalline silicon, creating sigma-shaped cavities in which epitaxy is grown.

The Crystal Etch process models crystallographic etching through the use of different etch rates for major silicon plane families. Fast and slow etch planes can be specified to adjust for different etching chemistries, and realistic CMOS source/drain profiles can be achieved when this feature is used in conjunction with the Selective Epitaxy process model.

SEMulator3D model of hydroxide-based etch results in exposed {111} facets.

Evolution of CMOS source/drain etch recess