3D Integrated Circuit (IC)

SEMulator3D can be used to explore the effect of process changes on 3D integrated devices.   For example, design technology co-optimization studies of on-chip power can be undertaken to improve the utilization density of next generation technologies.

IR-drop in the logic power grid has become a limiting factor to scaling, because of metal resistance approaching ~1kΩ/um. The on-die power grid is constructed over several metal layers and may also consist of power switches for core shut down function.  A significant portion of the voltage drop across the grid occurs due to the highly resistive standard cell power rails. One alternative option is to use buried power rail (BPR) standard cell libraries, which have a power rail engineered to have a resistance of 50Ω/um. The adoption of buried power rails in the logic libraries can result in a significant increase in utilization and can decrease the logic core area requirements at roughly equivalent voltage drop targets. An outline of the buried power rail technology and some silicon data is shown in Figure 1.

Illustration of Buried Power Rail technology

Figure 1. Illustration of Buried Power Rail technology (courtesy: imec)

The introduction of a new interconnect scheme does not fully solve the problem of IR drop and utilization loss, since the power grid is still used in the standard BEOL. Therefore, a new interconnect scheme was developed by imec through the backside of the active die to deliver power from external power bumps.


3D integrated logic technology

Figure 2. Process Flow for proposed Backside Power Delivery Network

The process steps for the proposed backside PDN are illustrated in Figure 2, using SEMulator3D. We start with a BPR-Logic device wafer, which is bonded to a carrier wafer and then thinned down to 500nm with minimal thickness variation. Next, patterning the high aspect ratio μ-TSV’s is accomplished via passivation, high aspect ratio etch, liner deposition and metal deposition, followed by a final chemical mechanical planarization step (CMP). The final device wafers have a standard metal stack, which is used only for signal routing.   The backside μ-TSV and the metal layers are used for the P/G grid. The sensitivity of the grid resistance to various process parameters, as modeled in SEMulator3D, is depicted in Figure 3.

3D IC process modeling

Figure 3. Resistance Sensitivity of Buried Power Rail to different process variables

In this work, the developers combined 3D – μTSV technology and logic technology to decouple the power grid from the design budget. The proposed technique delivers power from the backside of a thinned device wafer using the process steps depicted in Figure 2. An analysis demonstrated significant area savings and IR-drop reduction. SEMulator3D was used to explore the effect of process changes on power rail resistance, and to gain an understanding of the impact of process variations to the Process of Record.

Interested in learning more?

Download the full whitepaper “Backside Power Delivery as a Scaling Knob for Future Systems” to read about how to understand the effect of process changes on new 3D integrated device designs.

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