Design Enablement

High quality design manuals, robust checking decks, and parasitic extraction tools are critical elements in enabling the design of semiconductor products. These Process Design Kit (PDK) artifacts are typically developed and validated in silicon during the early phases of technology development. However, early in the development of technologies, the process flow is often unstable and hardware validation usually delivers inconclusive results. Using a predictive virtual fabrication platform to develop and validate design rules and structures can speed the production of PDKs, and ensure robust checking decks for early technology adopters.

Design Rule Development

Design rules have become increasingly difficult to develop as technology has become more complex, and often design rules are now specified for specific design constructs. Compare, for example, the cases of a via (V1) placed at the crossing of the metal level above (M2) and the metal level below (M1) vs. the case of a via placed at adjacent corners of those same metal levels. The crossing case, in this self-aligned via technology example, has no strong sensitivity to M2 overlay errors. The contact area between V1 and M1 is dictated by V1 overlay errors.

Analysis of V1-M1 interface in a (a) crossing design construct, showing (b) the SEMulator3D predictive structural model of the nominal case, and (c) the interface area sensitivity to V1 lithographic overlay tolerance

Figure 1. Analysis of V1-M1 interface in a (a) crossing design construct, showing (b) the SEMulator3D predictive structural model of the nominal case, and (c) the interface area sensitivity to V1 lithographic overlay tolerance

However, in the case of the adjacent corners, the V1 contact area to M1 is dictated by both M2 overlay errors and V1 overlay errors. In this case, under the same set of overlay variations, the contact area is significantly reduced relative to the crossing case. If this reduction exceeds a yield or reliability criterion, then this design construct must be prohibited.

Analysis of V1-M1 interface in an (a) adjacent corner design construct, showing (b) the SEMulator3D predictive structural model of the nominal case, and (c) the interface area sensitivity to M1 lithographic overlay tolerance without V1 overlay errors, and (d) further reduction of interface area when V1 overlay errors are included

Figure 2. Analysis of V1-M1 interface in an (a) adjacent corner design construct, showing (b) the SEMulator3D predictive structural model of the nominal case, and (c) the interface area sensitivity to M1 lithographic overlay tolerance without V1 overlay errors, and (d) further reduction of interface area when V1 overlay errors are included

This type of analysis is typically accomplished using spreadsheet calculations and various process assumptions. These process assumptions are not inherently predictive, like the SEMulator3D virtual fabrication platform, and therefore often lead to inaccurate predictions. The virtual fabrication platform can develop this type of design-sensitive rule analysis simply, and in a physically predictive sense, to produce more robust, high quality design rule checking.

Process Tolerance Modeling

Process variations must be well understood to achieve yield in advanced technologies, and also should be properly reflected in models and extraction decks in order for designers to accurately predict electrical behavior. Consider the case of self-aligned contacts, where etch selectivity provides yield robustness in the face of lithographic overlay variation. This self-alignment also severely limits the contact area to the source/drain regions, increasing parasitic resistance. Trying to extract this type of variation sensitivity from hardware results can be clouded by other sources of variation. Combining the predictive modeling capabilities of SEMulator3D with Virtual Metrology and Expeditor, the key physical parameters governing this electrical behavior can be extracted.

SEMulator3D predictive physical model of contacts under nominal conditions (no contact overlay error), (b) TEM image from literature showing effect of contact overlay error, (c) SEMulator3D model under similar overlay error conditions and (d) source/drain contact area from Virtual Metrology for various overlay conditions explored in Expeditor

Figure 3. SEMulator3D predictive physical model of contacts under nominal conditions (no contact overlay error), (b) TEM image from literature showing effect of contact overlay error, (c) SEMulator3D model under similar overlay error conditions and (d) source/drain contact area from Virtual Metrology for various overlay conditions explored in Expeditor

Parasitic Extraction

Device parasitics are typically applied to designs using tools that combine 2D design data and reference simulation values. The reference data for these tools must be properly modeled from a structurally accurate physical representation. SEMulator3D has the capability to produce meshes for finite element analysis based on its process-predictive physical models. Parasitic values extracted from SEMulator3D models are significantly more accurate than those from the idealized models typically used.  SEMulator3D  provides both RC extraction and netlisting capabilities, including parasitic value extraction, and allows the netlist to be directly imported into a compact model.

SEMulator3D models showing (a) material view for completed FinFET FEoL and MOL of pull-up PFET and pull-down NFET from a 0.074um2 SRAM cell, (b) electrical view with colors representing individual electrical nets, (c) 3D volume meshed output with mesh refinement and (d) parasitic capacitance results from an external field solver

Figure 4. SEMulator3D models showing (a) material view for completed FinFET FEoL and MOL of pull-up PFET and pull-down NFET from a 0.074um2 SRAM cell, (b) electrical view with colors representing individual electrical nets, (c) 3D volume meshed output with mesh refinement and (d) parasitic capacitance results from an external field solver

Process Window Optimization

To ensure success in semiconductor technology development, process engineers and designers must set the allowed ranges for process parameters.  These specifications include critical dimensions, electrical performance requirements, and other device characteristics.  Cross-correlation and analysis of thousands of test data points is often required to optimize and calibrate process parameters of interest, and meet device specifications. Reducing the number of pre-production test wafers required to set the optimal process parameter ranges (known as the “process window”) will dramatically reduce the cost and risk of semiconductor technology development.

The Process Window Optimization feature of SEMulator3D can provide an optimized value of process parameters of interest, maximizing the percentage of the selected fabrication/device parameters that meet their metrology specifications (“in-spec percentage” or “inSpec%).

For example, in one PWO study of SAQP patterning, patterned lines and spacing were measured by virtual metrology and were all targeted at 16nm with a success criterion of +/-10%. We only varied two parameters in this study: the thicknesses of spacer 1 and spacer 2. Spacer 1 and Spacer 2 nominal targets were set at 13.5 nm and 18.8nm, respectively, with the same standard deviation of 0.2nm. The search spaces were defined for those two parameters as 11.7nm to 15.3nm and 17nm to 20.6nm, respectively. A total of 1000 runs were executed.  Figure 5 displays a graph containing all process parameter combinations considered in the DOE (with each point representing one run). The blue points represent runs which fulfilled the success criterion of having all metrology measurements at 16nm +/-10%.

Design of Experiment for Semiconductor Process Window Optimization (PWO)

Figure 5. DOE illustration with all runs executed and successful runs highlighted in blue

As shown in Figure 6, assuming a 0.2nm standard deviation for spacer 1 and spacer 2 thicknesses, the PWO system reported an increase in metrology in-specification percentage from 69.6 to 74.6% (maximized) when changing the spacer 1 nominal value from 13.5nm to 13.4nm and spacer 2 nominal from 18.8nm to 18.9nm. Moreover, reducing the spacer thickness standard deviation from 0.2nm to 0.18nm increased the metrology in-specification percentage to 85.1%.

PWO reporting for % in-specification value, based upon mean standard deviation values for each process parameter

Figure 6. PWO reporting for % in-specification value, based upon mean standard deviation values for each process parameter

Conclusion

The SEMulator3D platform for virtual fabrication provides a powerful new way of developing PDKs for advanced technology nodes. Use of the platform for design rule development and parasitic extraction can save months of time in producing PDKs for new technologies. The time savings are a huge benefit to both early adopters and foundries.

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