MEMS Design Verification
MEMS and semiconductor manufacturing design rules are typically enforced using 2D design rule checks (DRC) on the device layout. However, some types of design and layout mistakes are not obvious in two dimensions, making it difficult to fully verify manufacturability and device performance. With SEMulator3D, engineers can catch these mistakes before running test wafers by using virtual manufacturing (process simulation) to verify that a device design is compatible with the manufacturing process. The 3D models generated by SEMulator3D are used by process engineers and design engineers to communicate the modifications required to either the design or the process.
- Verify design manufacturability
- Find design mistakes not caught by standard 2D DRC
- Quickly test-build multiple design variations
- Optimize device designs for a manufacturing process
- Streamline design and manufacturing communications
Learn how to share 3D models with the SEMulator3D Reader.
Behavioral Verification with SEMulator3D
MEMS designs are often developed using either finite element simulation or reduced-order modeling techniques. Because creation of 3D geometry for simulation can be difficult, most simulations are performed using idealized geometry. But, as designs move into manufacturing, the structures created in the fab can differ significantly from the idealized geometry used during the initial design phase. This discrepancy between predicted performance and actual device performance results in costly re-design and additional test wafer runs.
SEMulator3D bridges the behavioral verification gap with 3D geometry and mesh generation using silicon-accurate models. By accurately modeling the manufacturing process, SEMulator3D creates realistic geometry that is difficult or impossible to capture using conventional solid modeling software. With SEMulator3D, engineers can automatically generate surface or volume meshes suitable for multi-physics simulations.
When combined with a multi-physics simulation package, SEMulator3D can:
- Verify device performance using silicon-accurate geometry
- Investigate how manufacturing effects change device performance
- Emulate lithography effects on device behavior
- Quickly test several design options
“SEMulator3D is invaluable for creating geometrically accurate 3D finite element meshes of semiconductor device and interconnect layers at the sub-micron and micron scale. Coupled with package models, the SEMulator3D mesh allows us to simulate stress evolution through wafer fabrication, packaging and temperature cycling. This provides more insight on the thermo-mechanical interactions, which gives us a measure of device reliability. Furthermore, design rules can be adjusted to reduce or avoid stress in critical areas.” – KAI GmbH