FinFET FEOL Technology Integration

Purely geometric scaling of transistors ended around the 90nm era. Since then, most power/performance and area/cost improvements have come from structural and material innovations, such as FinFETs. Unfortunately, massive, time-consuming, resource-intensive technology development efforts have been required to bring FinFETs into production. Virtual fabrication with SEMulator3D can dramatically reduce the time and resources required to develop an integrated process flow for FinFET Front End of Line (FEoL).

Nominal Process Flow Development

Consider as an example an SRAM cell that must fit in an area consistent with published sub-22nm technology nodes: 0.074um2 [1]. Assumptions on critical design rules, such as 86nm SRAM gate pitch, can be made in order to fit the cell design into six tracks of 72nm pitch wiring.

Figure 1. Design data for an example 0.074µm2 SRAM cell

Several publications on FinFETs [2] provide sufficient information to build up an integrated, nominal flow in SEMulator3D. The 3D views in Figure 2 show the state of the SRAM cell after key stages in the integrated flow.

Figure 2. SEMulator3D model output after (a) Fin Definition and STI, (b) sacrificial gate module, (c) spacers and embedded SiGe, (d) Replacement Metal Gate and (e) Middle of Line modules

Model Calibration and Verification

To make SEMulator3D models predictive, individual processes and integrated process flows must be calibrated. Typical in-fab technology development efforts produce ample data for calibrating and verifying SEMulator3D models. Our example SRAM cell has been calibrated with readily available characterization data [3]. For instance, the epitaxial PFET SiGe source/drain region is a recognizable feature in published FinFET technology. Accurate modeling of selective epitaxy must allow for different growth rates of the major crystal planes.

Figure 3. Cross-sectional comparison of SiGe embedded stressor profile from (a) published literature and (b) SEMulator3D model

The complex integration of the replacement metal gate must be properly modeled as well. This module demands accurate modeling of depositions and the dual-metal integration demands accuracy for etch/clean processes that impact large groups of materials.

Figure 4. Cross-sectional comparison of Replacement Metal Gate stack between (a) published literature and (b) SEMulator3D model

Predictive Modeling of Source/Drain Embedded Epitaxy

The integration of embedded stressors has become extremely complex for FinFET technology, but remains essential for achieving transistor performance goals. The details of the processes before the epitaxy, including any erosion or etching of the silicon fin, have a large impact on the final structure. The real value of virtual fabrication with SEMulator3D becomes apparent after the integrated process flow has been calibrated. The results of a virtual experiment, performed by varying behavioral parameters in the process flow, are shown below.

Figure 5. Results of a SEMulator3D virtual experiment on PFET source/drain selective SiGe epitaxy show the structural implications of pre-epitaxy fin erosion/etch, epitaxial target thickness and relative growth rates of major crystal planes

Figure 6. SEMulator3D models showing selected results from PFET source/drain selective SiGe epitaxy experiment, and describing the location of the width measurement

The results demonstrate a strong structural dependence on the processes before the actual epitaxy. The cross sectional area of the final SiGe stressor is dominated by the amount of fin erosion by etching prior to epitaxy. Differences of 2nm in the erosion act to nearly double the stressor cross-sectional area, and could result in a critical performance impact. This study covered a full-factorial, 243-way experiment and required six hours of computation running on a four-core PC. A similar study in the fab would have taken hundreds of fully integrated wafers and months of process and characterization time.


The virtual experiment on the source/drain embedded epitaxy process module demonstrates that SEMulator3D is predictive tool for process integration that can replace costly and time-consuming cycles of silicon learning during the integration and yield-ramp phases of FinFET FEoL technology development. For a more detailed explanation of this example and further examples of the predictive value of SEMulator3D, request a copy of the white paper FinFET Front End of Line Process Development.


[1] Wood, O; Sematech website (
[2] Auth, C.; VLSI Symposium on Technology, June 2012
[3] Narasimha, S.; International Electron Devices Meeting, December 2012

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