FinFET FEOL Technology Integration
Purely geometric scaling of transistors ended around the 90nm era. Since then, most power/performance and area/cost improvements have come from structural and material innovations, such as FinFETs. Unfortunately, massive, time-consuming, resource-intensive technology development efforts have been required to bring FinFETs into production. Virtual fabrication with SEMulator3D can dramatically reduce the time and resources required to develop an integrated process flow for FinFET Front End of Line (FEOL).
Nominal Process Flow Development
Consider as an example an SRAM cell that must fit in an area consistent with published sub-22nm technology nodes: 0.074um2 . Assumptions on critical design rules, such as 86nm SRAM gate pitch, can be made in order to fit the cell design into six tracks of 72nm pitch wiring.
Several publications on FinFETs  provide sufficient information to build up an integrated, nominal flow in SEMulator3D. The 3D views in Figure 2 show the state of the SRAM cell after key stages in the integrated flow.
Model Calibration and Verification
To make SEMulator3D models predictive, individual processes and integrated process flows must be calibrated. Typical in-fab technology development efforts produce ample data for calibrating and verifying SEMulator3D models. Our example SRAM cell has been calibrated with readily available characterization data . For instance, the epitaxial PFET SiGe source/drain region is a recognizable feature in published FinFET technology. Accurate modeling of selective epitaxy must allow for different growth rates of the major crystal planes.
The complex integration of the replacement metal gate must be properly modeled as well. This module demands accurate modeling of depositions and the dual-metal integration demands accuracy for etch/clean processes that impact large groups of materials.
Predictive Modeling of Source/Drain Embedded Epitaxy
The integration of embedded stressors has become extremely complex for FinFET technology, but remains essential for achieving transistor performance goals. The details of the processes before the epitaxy, including any erosion or etching of the silicon fin, have a large impact on the final structure. The real value of virtual fabrication with SEMulator3D becomes apparent after the integrated process flow has been calibrated. The results of a virtual experiment, performed by varying behavioral parameters in the process flow, are shown below.
The results demonstrate a strong structural dependence on the processes before the actual epitaxy. The cross sectional area of the final SiGe stressor is dominated by the amount of fin erosion by etching prior to epitaxy. Differences of 2nm in the erosion act to nearly double the stressor cross-sectional area, and could result in a critical performance impact. This study covered a full-factorial, 243-way experiment and can be completed within a few hours computation time. A similar study in the fab would have taken hundreds of fully integrated wafers and months of process and characterization time.
This virtual experiment on a source/drain embedded epitaxy process highlights how SEMulator3D can be used as a predictive tool for process integration. SEMulator3D can replace costly and time-consuming cycles of silicon learning during the integration and yield-ramp phases of FinFET FEOL technology development.
 Wood, O; Sematech website (www.sematech.org)
 Auth, C.; VLSI Symposium on Technology, June 2012
 Narasimha, S.; International Electron Devices Meeting, December 2012
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