Dynamic Random Access Memory (DRAM) is an efficient, high-performance memory solution that can be found in most modern electronics, such as laptop computers, servers, graphics cards, consumer products and mobile devices. Each DRAM cell is a comprised of a capacitor attached to a transistor, and requires periodic refreshing to retain its memory state. DRAM chip capacities have risen exponentially (and DRAM price per bit has decreased exponentially) over time, through innovations in DRAM cell density and packaging. Much of this success can be attributed to innovative lithography, patterning and manufacturing technologies that have enabled increased DRAM density.
SEMulator3D can be used to model the effect of process changes on innovative DRAM device structures. For example, DRAM electrical performance can be analyzed based upon process variations such as etch material selectivity or etch flux distribution. This page contains a simple case study, to highlight the effect of DRAM geometry on electrical performance and yield.
Using public data, a nominal calibrated process flow was established for a 2X DRAM in SEMulator3D. This process flow was then used to generate a 3D predictive structural representation of the device technology (Figure 1).
Electrical Device Simulation
Once the model was configured, electrical analysis was undertaken. The process flow ends at the capacitor contact (CC), which is sufficient to enable electrical analysis and study edge effects in the capacitor.
SEMulator3D identifies device ports and electrodes in the 3D structure and simulates device characteristics, such as temperature, bandgap and electron/hole mobility. We can automatically extract metrics of interest, such as threshold voltage (Vth), sub-threshold slope, drain-induced barrier lowering (DIBL) and ON current (ION) at a voltage point, and perform voltage sweeps like those shown in Figure 2. The electrical analysis takes into account actual 3D process effects on device performance.
Impact of Geometry Change
We might then look at the impact of a change in DRAM device geometry on electrical performance. We start with a nominal model (Figure 3, left) containing targeted hardmask CD/top CD, silicon depth and oxide depth. SEMulator3D can then use these nominal device geometry values and extract the resulting electrical characteristics of the device, including Vt, ION, IOFF and sub-threshold slope under changing geometries.
Next, we choose the hardmask (top) CD as our study parameter. We vary the hardmask CD from 12 nm to 30 nm in 2 nm increments, while monitoring the remaining structural parameters such as silicon depth and oxide etch. This change is made by varying the etch process step early in the process flow. The downstream process steps respond predictively to these changes within the model.
Figure 3 (right) highlights that changes in hardmask CD create a non-linear electrical response. Oxide depth and top silicon depth are sensitive to top CD at smaller CDs, but saturate at larger CDs. On the other hand, Vtsat increases significantly with changing CD above the nominal 20 nm value. The SEMulator3D DRAM model displays a complex electrical device response to a single change in geometry. This type of analysis provides engineers with powerful tools to study the impact of a proposed geometry or process change on DRAM performance.
Interested in learning more?
Download the full whitepaper “Speeding Up Process Optimization with Virtual Fabrication Modeling” to learn more about identifying critical process steps and corner cases in DRAM development.