45nm High-K Metal Gate Logic Technology

45nm High-K Metal Gate Logic Technology model for SEMulator3D Reader, 68.7 MB
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Intel presented its new 45nm logic technology at the IEDM conference in Washington, DC in 2007. The transistors featured several significant technology changes, including:

  • Hafnium-based, high-k gate dielectric
  • Dual work-function metal replacement gate
  • Enhanced channel strain

The combination of a high-k dielectric and metal gates provided a significant reduction in gate leakage relative to prior technology nodes. PMOS performance was also improved by increasing channel strain, implemented with an increased Ge fraction in SiGe regions for source and drain in the PMOS transistor.


Figure 1: SEM image (courtesy of Intel) and cross section of SEMulator3D model for the Intel 45nm PMOS device.

With the exception of the high-k dielectric, the first part of the process is similar to older technology nodes and includes shallow trench isolation, channel implants for threshold voltage, atomic layer deposition for the high-k gate dielectric, and a polysilicon gate conductor layer. Both NMOS and PMOS receive a shallow extension implant.


Figure 2: 45nm transistor gate stack showing high-k dielectric (yellow), temporary gate polysilicon and extension implant.

The next step is the formation of the spacer and SiGe formation for the PMOS device. The SiGe process involves etching a recess on both sides of the gate, followed by epitaxial SiGe growth.


Figure 3: 45nm PMOS transistor after epitaxial SiGe growth. The resist (red) isolates PMOS devices during the SiGe process. The spacer is undercut slightly during the recess etch, producing a notch in the SiGe profile that is visible in the SEM and accurately modeled with SEMulator3D.

After SiGe formation, high-dose implants define the source and drain regions, followed by silicidation and the first ILD layer (ILD0). The metal gate is formed by polishing the ILD layer down to the top of the polysilicon gate material, followed by removal of the polysilicon. This leaves an open gate area that will be filled with gate metal.


Figure 4: 45nm PMOS transistor after removal of the gate polysilicon for which SEMulator3D is able to model the CMP dishing.

The first metal deposit on the gate area is the PMOS work function metal, followed by the NMOS work function metal (the PMOS metal is removed from NMOS transistors prior to deposition of the second work function metal). The remaining gate space is filled with aluminum and excess is polished away to leave a finished high-k metal gate transistor.


Figure 5: 45nm PMOS transistor with completed metal gate

45nm CMOS process

The 3D models shown here were created by Coventor through the study of publicly published information about the Intel 45nm CMOS process. No proprietary information was used to create these models or images.


[1] K. Mistry et al, “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”, Proc. IEDM 2007, pp. 247-250.
[2] http://www.intel.com/pressroom/kits/45nm/photos.htm

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