By: Pradeep Nanja, Software Applications Engineer
As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects such as peeling (or delamination), particle contamination, arcing, and micromasking to improve yield. We will now review these defects in detail and discuss ways to prevent them. read more…
By: Steve Shih-Wei Wang, PhD, SP&I Engineer
Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC . Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC . According to recent news reports, vendors are already working on next generation 3D NAND that contains even more layers. What are the 3D NAND’s process challenges, and what might be its ceiling, as increasing numbers of layers are used?
Figure 1: 3D NAND Memory Array and Key Process Challenges (Source: Lam Research)
New in SEMulator3D 7.0: Powerful new process and device simulation capabilities
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Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0
New Features Enable SEMulator3D Version 7.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development
CARY, NC– February 28, 2018 – February 26, 2018 – Coventor, Inc., a Lam Research Company, the leading supplier of design automation solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 7.0 – the newest version of its semiconductor virtual fabrication platform. With added features, performance improvements, and a new Device Analysis capability, SEMulator3D 7.0 addresses both process and device simulation while lowering the barriers to advanced semiconductor technology development. The new Device Analysis capability enables seamless understanding of how process changes, process variability, and integration schemes directly impact transistor device performance. read more…
Tagged 3D NAND, Coventor, device analysis, FinFET, FinFET Technology, FinFET transistor performance, lithography, lithography modeling, multi-patterning, NAND, Netlist, Netlist Extraction, Press release, Process Development, Process Integration, Process Modeling, Process Simulation, Process Variability, Process variation, semiconductor patterning, semiconductor process flow, semiconductor process modeling, semiconductor process variation, SEMulator 3D, SEMulator3D, SPICE simulation, TCAD, transistor device performance, transistor IV curves, transistor performance, virtual fabrication
Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology. The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes. Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.
L-R: Ed Sperling (moderator), Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt
Tagged 10NM, 2NM, 3D NAND, 3D XPOINT, 3NM, 5NM, 7NM, ASML, BEOL, DRAM, ETCH, EUV, FINFETS, GATE-ALL-AROUND FETS, GLOBALFOUNDRIES, INSPECTION, KLA-TENCOR, LAM RESEARCH, lithography, METROLOGY, Moore's Law, MRAM, NANOSHEETS, NOVA MEASURING INSTRUMENTS, PHASE-CHANGE MEMORY, RERAM, RESISTANCE, STRESS, STT-RAM, THIN FILMS, VON NEUMANN ARCHITECTURE
By Mark Lapedus
Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.
SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?
Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.
read the full article here
Tagged 10NM, 3D NAND, 5NM, ATOMIC-LEVEL VARIABILITY, BEOL, Coventor, DEPOSITION, Directed Self Assembly, DSA, ETCH, EUV, III-V MATERIALS, INTEL, lithography, LOW-K DIELECTRICS, MRAM, multi-patterning, NANOWIRE FETS, RC DELAY, RERAM, SADP, TSMC