Challenges and Solutions for Silicon Wafer Bevel Defects during 3D NAND Flash Manufacturing

By: Pradeep Nanja, Software Applications Engineer


As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects such as peeling (or delamination), particle contamination, arcing, and micromasking to improve yield. We will now review these defects in detail and discuss ways to prevent them.


From 2-3mm out to the wafer’s edge, there are five regions of concern: the wafer top edge, the upper bevel, the apex, the lower bevel, and the wafer bottom edge (see Figure 1) [1].

Figure 1: Various areas of the wafer beyond the active or patterned area

Figure 1: Various areas of the wafer beyond the active or patterned area

Manufacturing standards have required polishing of the bevel region to prevent wafer cracking and chipping. At the edge area between the flat surface and the curved region of the wafer, the materials are deposited with non-uniform thickness and etched at various rates [2]. During etching, some of these materials may be improperly removed at the edge and some of the residue particles or etching polymer can land back on the bevel or backside of the wafer. This accumulation of particles and materials can lead to peeling or delamination of the wafer, with subsequent yield loss.

Types of Defects

Peeling (or Delamination) or Particle Defects:

During the semiconductor manufacturing process, there are many ways that peeling or particle contamination can occur. The films that are deposited during semiconductor manufacturing wrap around the edge, bevel area, and apex. Since subsequent dry etches are not isotropic, they can remove some stacks at the edge but not completely around the bevel or apex region [3]. Therefore, the remaining stacked films can have interfacial stress that prevents them from adhering properly. Annealing steps will cause the film adhesion to degrade as the material properties change during the heating and cooling process. This can cause blisters to form and these blisters can continue to grow further through thermal expansion. If the blisters are broken by wafer handling, additional particles can be created. Wet etch processes can also attack the thin surfaces on the wafer edge, resulting in delamination that creates more particles. This is a severe defect since these particles can potentially land on the center of the wafer and increase yield loss [4]. Peeling can also occur in 3D NAND as the carbon deposition, especially with memory hole and staircase patterning, is very thick and has potential to break off and become a peeling source.


Arcing is the electrical breakdown of a gas that produces a prolonged electrical discharge. There are process steps that require reactive ion etching and tungsten (W) fill where arcing can occur. The problem of arcing or electrical discharge of the plasma is particularly noticeable in RIE processes. Arcing damage can occur due to unequal charge distribution in low dielectric insulating layers during high aspect ratio RIE.  The arcing damage tends to occur near metallization lines, which act as a ground path to charged areas in the dielectric insulating layer. Multiple layers of thin interlayer dielectric (ILD), metal barrier (TiN) and conductor films (W) can form at the wafer edge with different thicknesses due to incomplete removal of residual particles. These residual particles create undesirable interfaces between different materials at varying locations on the wafer, causing a charge buildup at the metallic interfaces where metal can be explosively vaporized [5]. This charge buildup leads to the ejection of metallic particles from the bevel area into the active area of the wafer, causing different types of shorts and significantly impacting yield. Therefore, a proper bevel etch is needed after metal deposition to remove any future possibility of destructive arcing during RIE. In addition, the carbon hardmask used in 3D NAND is conductive and should be removed as it can also be an arcing source.

Micromasking or needle-like defects:

Micromasking or needle-like defects are seen during any high aspect ratio etch process, such as those used in producing DRAM, NAND, and power devices.  The scaling of 3D NAND flash has exacerbated this specific defect. These defects occur at the bevel region, if the etched material is exposed at the bevel during the etch process. In floating gate OPOP (Oxide-Poly Si-Oxide-Poly Si) gate first integration, the memory hole etch is non-selective to substrate and severe micromasking at the bevel region can occur during the memory hole and slit etch. In charge trap ONON (Oxide-Nitride-Oxide-Nitride) replacement gate integration, the memory hole and slit etch is selective to the silicon substrate. Micromasking at the bevel can be mitigated by carefully applying a bevel etch step, to prevent it from occurring at the oxide-nitride layer. During ONON integration, the nitride is removed and subsequently replaced with tungsten. This nitride exhume step can cause defects at the bevel through wet undercut, especially if the prior high aspect ratio etch step creates micromasking in that region.

Bevel Etch Process

The bevel etch process is used to remove any type of film on the edge of the wafer, whether it is a dielectric, metal, or organic material film. During this process, the wafer is held by a top and bottom plate so that the wafer edge is the only exposed part of the wafer (see Figure 2) [6]. This ensures that only the edge of the wafer is etched.

Figure 2: Picture of the frontside region and backside region of the bevel edge that will be exposed for etching

Figure 2: Picture of the frontside region and backside region of the bevel edge that will be exposed for etching

During bevel etch, N2 flows away from the center of the wafer toward the edge. This prevents particles from being pushed to the center of wafer that could contaminate the wafer and create yield issues. The positioning of any bevel etch is critical, since a mistake could cause a thickness variation problem on the wafer. The bevel etch helps reduce defect density at the edge of the wafer, by preventing peeling, arcing and micromasking problems.


Mitigating edge defects is a key aspect of increasing yield when technology is scaled down and complexity increases. Understanding edge defects such as peeling, arcing and micromasking will be critical to improving wafer yield. These specific defects can be mitigated by adding bevel etch and bevel clean processes at specific points in the process flow. The bevel etch and bevel clean processes will be critical at future technology nodes, and we can expect to see an increase in the number of these processes as our integration challenges increase.

Note: The Coventor team will publish future articles about modeling of bevel defects, to highlight failure modes and potential solutions.


[1] Porat, Ronnie, et al., “SEM-based methodology for root cause analysis of wafer edge and bevel defects,” IEEE/SEMI/ASMC Meeting, 2008.

[2] Yavas, O., Richter, E., Kluthe, C., and Sickmoeller, M., “Wafer-edge yield engineering in leading-edge DRAM manufacturing,” Semiconductor Fabtech., Vol. 39, pp. 1-5, 2009.

[3] Morillo, J.D., Houghton, T., Bauer, J.M. (IBM), Smith, R., Shay, R. (Rudoph Technologies), “Edge and Bevel Automated Defect Inspection for 300mm Production Wafers in Manufacturing,” Semiconductor Manufacturing Magazine, June 2005.

[4] Burkeen, F., Vedula, S., Meeks, S. (KLA Tencor), “Visualizing the Wafer’s Edge,” Spring 2007 Yield Management Solutions.

[5] Bunke, C., Houghton, T., Bandy, K., Stojakovic, G., Frang, G., “Bevel RIE Application to Reduce Defectivity in Copper BEOL Processing,” 23nd Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), ISSN: 1078-8743, 2012.

[6] Tran, Stephen, et al., “Process induced wafer geometry impact on center and edge lithography performance for sub 2x nm nodes,” AMC 2015, Proc. Of Advanced Semiconductor Manufacturing Conference (IEEE/SEMI), pp. 345-350, 2015.

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3D NAND: Challenges beyond 96-Layer Memory Arrays

By: Steve Shih-Wei Wang, PhD, SP&I Engineer

Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC [1]. Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC [2]. According to recent news reports, vendors are already working on next generation 3D NAND that contains even more layers. What are the 3D NAND’s process challenges, and what might be its ceiling, as increasing numbers of layers are used?

Figure 1: 3D NAND Memory Array and Key Process Challenges (Source: Lam Research)

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Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0

New in SEMulator3D 7.0:  Powerful new process and device simulation capabilities


For Immediate Distribution
For more information, contact:
Toni Sottak
(408) 876-4418,

 Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0

New Features Enable SEMulator3D Version 7.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development

CARY, NC– February 28, 2018 – February 26, 2018 – Coventor, Inc., a Lam Research Company, the leading supplier of design automation solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 7.0 – the newest version of its semiconductor virtual fabrication platform. With added features, performance improvements, and a new Device Analysis capability, SEMulator3D 7.0 addresses both process and device simulation while lowering the barriers to advanced semiconductor technology development.  The new Device Analysis capability enables seamless understanding of how process changes, process variability, and integration schemes directly impact transistor device performance.   read more…

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What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology.  The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes.  Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.

The Next 5 Years of Semiconductor Technology

L-R: Ed Sperling (moderator), Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt

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Inside Process Technology


By Mark Lapedus

Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.

SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?

Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.

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