July 31, 2019
Top view of slit and channel hole at different nodes

Advanced Patterning Techniques for 3D NAND Devices

Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market […]
May 21, 2019

Challenges and Solutions for Silicon Wafer Bevel Defects during 3D NAND Flash Manufacturing

As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer […]
February 4, 2019
Wedge Cutaway and Schematic – 3D NAND Device

Innovative Solutions to Increase 3D NAND Flash Memory Density

3D NAND flash memory has enabled a new generation of non-volatile solid-state storage useful in nearly every electronic device imaginable. 3D NAND can achieve data densities exceeding those of 2D NAND […]
October 12, 2018
3D NAND Memory Array and Key Process Challenges (Source: Lam Research)

3D NAND: Challenges beyond 96-Layer Memory Arrays

Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the […]
February 28, 2018
New in SEMulator3D 7.0: Powerful new process and device simulation capabilities

Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0

New Features Enable SEMulator3D Version 7.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development CARY, NC– February 28, 2018 – February 26, […]
December 19, 2017
2017 IEDM Panel Speakers on Stage

What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology.  The panel discussed alternative methods […]
March 12, 2015
Example of a 3D NAND flash memory array.

Defect Evolution in 3D NAND Flash

3D NAND Flash has become a hot topic in non-volatile memory these days. While planar NAND flash is still going strong, it has been increasingly difficult to scale planar technology […]
May 23, 2014
3D NAND flash memory array, based on TCAT [1], with 16 cells per string, top gate-select layer and bottom source-select layer.

Challenges in 3D NAND Flash Processing

With 2D planar NAND flash hitting scaling issues at sub-20nm technology nodes, 3D NAND flash has become all the rage. Instead of restricting memory cells to a single plane and […]
September 29, 2013

When will we get 3D NAND Flash Memory???

It’s about time for 3D NAND Flash, the agreed-upon “future of memory technology” to stop being the future and start being the present. The concepts all make sense. DRAM scaling […]
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