Practical Methods to Overcome the Challenges of 3D Logic Design

By:  Benjamin Vincent, Ph.D., Staff Engineer, Semiconductor Process & Integration

What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start stacking them on top of each other!

The Challenge: How can we shrink logic devices?

Logic designers are currently facing even bigger challenges than you might be having in tidying up your storage area. Not only are logic cells highly packed together already, but in addition their sizes are constantly required to shrink. Logic designers can increase the density of devices by re-engineering logic to generate new white space areas on their logic cells. This white space can be subsequently removed, in effect increasing the density of the device. When component (transistor) level scaling cannot shrink sizes any further, designers need to find other scaling boosters. Luckily, logic designers have another alternative to increase the density of their designs. We live in a 3D world, and we can think about designing in 3 dimensions to increase device performance over that of current 2D designs. read more…

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